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37-A sequencing-based taxonomy of I0 systems and review of Historical Machines.pdf

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37-A sequencing-based taxonomy of I0 systems and review of Historical Machines.pdf

ASequencingBasedTaxonomyofI/OSystemsandReviewofHistoricalMachinesMarkSrnothermanDept.ofComputerScienceClemsonUniversity,Clemson,SC296341906INTERNETmarkhubcap.clemson.eduAbstractAnewtaxonomyforI/OsystemsisproposedthatisbasedontheprogramsequencingnecessaryforthecontrolofI/Odevices.AreviewofhistoricalmachinesdemonstratestheneedforamorecomprehensivecategorizationthanpreviouslypublishedandrevealsthehistoricalfirstsofI/OinterruptsintheNBSDYSEAC,DMAintheIBMSAGEAN/FSQ7,theinterruptvectorconceptintheLincolnLabsTX2,andfullysymmetricI/OintheBurroughsD825multiprocessor.IntroductionTextbookpresentationsofI/Osystemstypicallyidentifyonlyfourcategoriesi.e.themethodsofdatatransfer1programcontrolledI/Oi.e.polling,2interruptdrivenI/O,3DMA,and4channelI/O.BlaauwandBrookspresentabroadercategorizationintheirmanuscript,ComputerArchitecture\10\.TheyidentifyessentiallysevendistincttypesofI/OsystemsI.DependentI/OA.directB.singleinstructionoverlap1.privatebufferperdevice2.sharedbuffera.dedicatedtoI/Ousageb.generalbufferinmainmemoryII.AutonomousI/OA.channelspecializedcontroller/processorB.peripheralprocessorgeneralizedprocessor1.homogeneousmulfiprocessorstructure2.heterogeneousmultiprocessorstructureHowever,afterreviewingthehistoricaldevelopmentofI/Osystems,Iamledtobelievethatthereisamuchricherdesignspaceandmoredifferencesbetweenmachinesthansuggestedbyeitherofthecategorizationsabove.Foruniprocessors,Ibelievethatthemajorissueisthemethodoftransferinitiationthus,majorcategoriesaresynchronousI/OversustheseveraldifferentwaysinwhichoverlappedI/Ooperationscanbeinitiated.Foreachoftheoverlappedoperations,Ibelievetheyshouldbesubdividedaccordingtotheirmethodofcompletionreporting.Furthermore,themajormultiprocessorissueofsymmetryinI/Oshouldbehandledseparately.ThemethodoftransferisanindicationoftheleveloffunctionalityoftheI/Osubsystem,thatis,howoftenandhowmuchtheCPUisinvolvedintheactualtransfer.ThisrangesfromtheCPUdoingalltosophisticatedperi5pheralprocessingunits,anditappliestoallinitiation/completionreportingcategories.Withinthisrange,IdrawadistinctionbetweenacontrollerthatcantransferonlyoneblockbeforerequiringCPUinterventionandacontrollerthatcantransfermultipleblocksinascatter/gathertypeofoperationinwhichtheblocksareidentifiedtothecontrollerbyachainofdescriptors.SomedesignersandauthorscallacontrollerwiththelattercapabilityanI/Ochannel.Indeed,BellandNewellcategorizecontrollerswithscatter/gathercapabilityasPios,sincetheyconsiderthechainofblockdescriptorstobeaseriesofjumpinstructions\8\.However,inthistaxonomyIreservethetermI/OchannelforaspecializedI/Oprocessorthatfetchesinstructionswithidentifiableopcodefields.Moreover,IalsousethedistinctionmadebyBlaauwandBrooksbetweenI/OchannelsandI/Oprocessors,whichisthegeneralabilitytocount.Thatis,anI/Oprocessorshouldhavetheabilitytomaintainalooporeventcountthatisunrelatedtothetransferofagivennumberofwordsorcharactersperblock.Formultiprocessors,themethodofinitiationisnotasimportantasthesymmetryoftheinitiationtherefore,thissymmetryorlackofitbecomesthebasisofthemajorcategories.Themethodofcompletionreportingisthebasisofsubcategories,andsymmetryininterruptionisexplicitlyidentified.AclassificationofhistoricalmachinesservestodemonstratetheusefulnessoftheproposedtaxonomyandalsoservesasaguidedtourofthehistoryofI/Osystems.ForoldermachineswithmultipleI/Ooptions,Ihavechosentoclassifythemaccordingtotheirestablishedusee.g.theIBMS/360hassynchronousI/Ocapability,butitisrarelyused.Somemulfiprocessorsappearinthefirstsectionthisisbecausetheyrepresentthefirstuseofagiventransferinitiationmethod.Notallcategoriesarepopulatedwithmachines.Thismaybetheresultofomissionsonmypart,orthecategorymayindeedbeunfruitful.Iwouldliketocharacterizethereasonsforthelatteroccurrence.ASequencingBasedTaxonomyI.CPUI/OINTERACTIONA.SynchronoustransferB.Asynchronoustransfer1.interlockedinstructiontostarttransfera.synchronizationbyinterlockb.synchronizationbypollingi.separateinstructionstopollandtransferdataii.controllertransferswordsofblocki.e.DMAiii.controllerwithscatter/gathercapabilityoftencalledanI/Ochanneliv.I/OchannelwithspecializedI/Oinstructionsetv.I/Oprocessorc.synchronizationbyinterrupti.separateinstructiontotransferdataii.controllertransferswordsofblocki.e.DMAiii.controllerwithscatter/gathercapabilityoftencalledanI/Ochanneliv.I/OchannelwithspecializedI/Oinstructionsetv.I/Oprocessor2.conditionalinstructiontostarttransfera.synchronizationbypollingb.synchronizationbyinterrupt3.mailboxdeposittostarttransferi.e.singleentrya.synchronizationbypollingb.synchronizationbyinterrupt4.queueinserttostarttransferi.e.multipleentriesa.synchronizationbypollingb.synchronizationbyqueueingc.synchronizationbyinterrupt65.asynchronousinstructiontostarttransfera.synchronizationbypollingb.synchronizationbyinterruptH.MULTIPROCESSORI/OA.Asymmetricinitiation1.synchronizationbypolling2.synchronizationbyasymmetricinterrupt3.synchronizationbysymmetricinterruptB.Symmetricinitiation1.synchronizationbypolling2.synchronizationbyqueueing3.synchronizationbyasymmetricinterrupt4.synchronizationbysymmetricinterruptAReviewofHistoricalMachinesI.CPUI/OINTERACTIONA.SynchronoustransferERA11031953wordatatimeinterlockedI/O\8\.BellandNewellandBlaauwandBrookscreditaUNIVACl103Aasthefirstcomputertousetheinterruptconcept\8,10\,inwhichabatchmachinewaspreemptedtostartdatacollectionfromaNASAwindtunnel\44\however,seealsotheUNIVACIandNBSDYSEAC.IBM7021953blockinterlockedI/O\5,6\.TheCPUstallswhileablockofcharactersistransferredfromanI/Odevicebuffer.The702introducedthecontrolunitconcept.IBM14011959\5,6\.Thismachinewasoriginallydesignedasaprintercontrollerbutfoundwidespreaduseasasmallbusinesscomputer.ItusesoneopcodeperI/Odevice,andtheseincludereadingacardintomemorylocations0to79,punchingacardfromotherlocations,andprintingfromathirdsetoflocations.TheCPUstallswhilethecharactersaretransferred.Anexampleofitseaseofuseisthatacardduplicatingprogramcanbewritteninabout20charactersandpunchedontoonecard.B.Asynchronoustransfer1.interlockedinstructiontostarttransfera.synchronizationbyinterlockUNIVACI1951bufferedI/O\8,23,56\.Thereisone60wordtapebufferforinputandoneforoutput.AninitialinputinstructionstartsthetransfertothebufferandthenreleasestheCPUforoverlappedinstructionexecutionasubsequentinputinstructiondumpsthebuffertomemory,startsthenexttransfer,andthenreleasestheCPU.IfasubsequentinputinstructionisissuedtooearlythenaninterlockstallstheCPU.I/OerrorshalttheCPU,andtheoperatormustdiagnosetheproblem.CoddcreditstheUNIVACIasoneoftheearliestmachinestobeequippedwithprograminterruptionsincehestatesthatanarithmeticoverflowwouldcausetheprogramtostop\17\Eckertalsomentionsseveralchecksthatcanstopthemachine\23\.However,interruptswereapparentlyneverusedforI/Ocompletion.IBM7011952copylogic\5,6,10,14,50\,Afteraninitialpreparetoreadorwriteinstruction,7theprogrammustissueacopyinstructionforeachwordinthetransfer.Aloopiscodedtoupdatethememoryaddressesandissuethecopies,andtheloopmayalsoperformsuperficialprocessingsuchascharactercodeconversion.ThecopyinstructionisinterlockedsothatanearlyissueisstalleduntiltheI/Odevicecanprovide/acceptthenextword.Atendoffilethecopyinstructioncausesaoneinstructionskip,andattheendofblockitcausesatwoinstructionskip.b.synchronizationbypollingi.separateinstructionstopollandtransferdataPDP119597.ThismachineprovidedconditionalskipsonI/Obufferregistercontents,whichareapparentlyusedtopollfortransfercompletion.PDP819657,8.Conditionalskipsoncontrolunitstatusregistersareusedforpolling.ii.controllertransferswordsofblocki.e.DMAWhirlwindI,1951Everettstates,Ingeneralthecomputercontinuestorunduringterminalequipmentwaittimes,butexplainsnofurther29.IBMSAGEorAN/FSQ7,started1952,operational1955DMAoperation3.I/Ooperationsstartblocktransfersofdatato/fromdrumbuffersthatproceedinparallelwithfurtherCPUoperations.Acontrollergeneratesthesequentialmemoryaddressesfortheblockanddecrementsacounter,whiletheCPUhasaconditionalbranchtotestcompletionofthetransfer.TransfersareinterlockedsothattheCPUissmiledifasecondtransferisattemptedbeforethepreviousoneends.Jacobsstatestheinput/outputI/Obreak,ormemorycyclestealing,wasintroducedinSAGE37,andSerrell,etal.,identifycomputationinparallelwithI/OasasignificantnewfeatureofSAGE48.seealsoUNIVAC1107iii.controllerwithscatter/gathercapabilityoftencalledanI/OchannelHoneywell8001963hardwareassistedmultiprogramming34,35,42,43.Thismachineimplementseightvirtualprocessors,eachhaving2programcountersandanindividualinterruptvectorbaseregister.Oneachmemorycyclethehardwarescansonaprioritybasisforactivityoneightinputcontrollers,theneightoutputcontrollers,andthentheCPU.WithintheCPUthehardwarescansthevirtualprocessorsinacyclicmannerwithvariousexceptionsformultiplememorycycleoperations.PapersareunclearaboutprogramI/Osynchronization.iv.I/OchannelwithspecializedI/OinstructionsetseeIBM709v.I/Oprocessorexampleunknownc.synchronizationbyinterrupti.separateinstructiontotransferdataNBSDYSEAC1954introducedI/Ointerrupt38,39.ThismachinehastwoprogramcountersanI/OsignalcausestheCPUtoswitchPCs.Abitineachinstructioncanforceaswitchback8betweenPCs.Coddstates,intheNBSDYSEACtheverysignificantstepwasmadeofextendinginterruptiontoinputoutputoperations\17\.LincolnTX21957papermultiplesequence\30\.Thismachinecontains33programcounterseachI/OdevicehasadedicatedPCandoperatesatafixedpriorityi.e.forerunnerofintetruptvector.Eachinstructionhasbreakanddismissbitsbreakisusedtoindicatepointsatwhichahigherprioritysequencecantakeover,whiledismissisusedtoallowlowerprioritysequencestoresume.BlaauwandBrooksclassifythismachineashavingPPUs\10\,butIseetheexplicitinstructionbitsasarecognitionofthesharingofasingleCPU.Thus,IconsiderthismachineclosertointerruptvectoringthantovirtualPPUs.PDP11959\7\.Bell,etal.,creditthe16channelsequencebreaksystemtoTX2influenceactualoperationnotdescribed\7\.ii.controllertransferswordsofblocki.e.DMAUNIVAC11071962\11,12\.ControllerusesasingleI/Ocontrolword,whichcontainsamemoryaddress,addressincrement/decrementflag,andawordcount.InterruptoccursonzerocountwhenspecifiedbyLoadChannelcommands.iii.controllerwithscatter/gathercapabilityoftencalledanI/OchannelIBM70701958priorityprocessingI/Ointerrupt\51\.AnI/OcompletioncausestheCPUtoswitchtoanuninterruptiblepriorityroutine,andthereturnaddressisstoredinaregister.Themachineprovidesscatter/gathercapabilityusingachainofrecorddefinitionwords.IBMSTRETCHstarted1954,delivered1961\10,15,22\.TheI/Oexchangeactsasabytemultiplexor.I/Ocompletionispartofacomprehensiveinterruptvectorfacility,inwhicheachvectorcontainsasingleinstructiontobeexecutedoutsidethenormalinstructioncycle.Theseinstructionscanbesingleinstructionfixupsorsubroutinecalls.Ingeneral,interruptnestingisallowedhowever,I/Oistreatedasasinglecause.iv.I/OchannelwithspecializedI/OinstructionsetIBM7091957introductionofchannelI/O\5,6,32\.TheCPUmustexecutetwoinstructionsinsequencetostartI/O.Areadselectorwriteselectinstructionisfirstusedtoselectagivendevice,andthenachannelspecificinstructionisusedtoresetandstartanyofthemaximumofsixchannels766s.Theaddressfieldoftheresetandstartinstructionisusedtocarrythechannelprogramaddress.SomedeviceselectinstructionsareinterlockedsothattheCPUisstalledifasecondselectisissuedbeforeapreviousoneends.Theresetandselectinstructions,however,immediatelyactuponthechannels,whichweremuchmoresophisticatedthanthelaterIBMS/360channels.PollingcanbeusedforI/Ocompletion,whileinterruptiondatachanneltrapisavailableasanextracostfeature.Apparently,allinstallationschosetousetheinterruptfeature\M.Rubinstein,personalcommunication\.IBM70901958\8,10\.Theoptionaldatachanneltrapfeatureofthe709architectureisincludedasstandardequipment.AninterruptvectorwithapairofsavedPCandnewPClocationsforeachchannelisusedtoresolveI/Ocompletiontraps.Thelaterversionchannels7909canthemselvesbeinterruptedbyexternaleventsandarecapableofdealingwithI/OretrieswithoutCPUintervention.v.I/OprocessorUNIVACLARCstarted1954,delivered1960\20,24,25\.Highlevelrequestpacketse.g.record9numberorkeyaresenttoanI/Oprocessor,whichalsoperformsservicessuchasdevicequeueing.Therequestingprocessorisinterruptedwhenitsrequestiscomplete.2.conditionalinstructiontostarttransfera.synchronizationbypollingexampleunknownb.synchronizationbyinterruptIBMS/3601964\1,810\.TheStartI/OinstructionsetstheconditioncodeaccordingtosuccessofinitiationpathmaybebusyandCPUmustperformqueueing,orerrormayexist.ChannelI/Oisthemethodoftransfer,butalesscomplexchannelinstructionsetisprovidedthanthatfor7090channels.3.mailboxdeposittostarttransfera.synchronizationbypollingCDC66001965virtualPPUs\8,28,47,54,55,57\.InthetypicalOSstructure,PPUsareassignedtodevicesandpollreservedmainmemorylocationsinputmailboxestodetermineI/Orequestsforthatdevice.Afterstartingadevice,aPPUwillpollthedeviceuntilcompletionandwillthenplaceacompletionnoticeinitsoutputmailbox.ProgramsrunningontheCPUcanpolltheoutputmailboxotherwise,theycanbesuspendeduntilthePPUrunningtheOSseesthecompletionnoticeandresumestheprogrambyanexchangejump.BeforeanoutputtransferthePPUmustmovethedatafromthesharedmainmemorytoitslocalmemory,likewiseafteraninputtransferthePPUmustmovethedatafromitslocalmemorytothesharedmainmemory.TheexecutionoftenvirtualPPUsisaccomplishedbytimesharingasingleexecutionunit.b.synchronizationbyinterruptexampleunknown4.queueinserttostarttransfera.synchronizationbypollingBurroughsB77001972\20,28,47\.ReservedlocationsexistinmainmemorythatdefineheadandtailpointerstoI/OdevicerequestqueuesandI/Ocompletionblockqueues.QueuemanipulationsbytheCPUandI/Omodulesareatomicactions.AnyIOMcanhandleanydevice,butastartI/OinstructionissuedbytheCPUbeginsIOMprocessingonaspecifieddevicequeue.IOMprocessingcontinuesuntilanerror,interrupt,oremptyqueue.TheCPUpollsthecompletionblockqueue,or,optionally,interruptscanbegeneratedoncompletionofeachrequest.seealsoIBMS/370XAwherepathbusyqueueingishandledbythechannelsubsystemb.synchronizationbyqueueingHoneywellSeries60Level641974\4\.MicrocodedsemaphoreoperationsareusedinI/Oprocessing.OnI/Ocompletion,thecontrollerinsertsacompletionmessageintoaqueueandsignalsthecorrespondinggeneralsemaphore.10ELXSISystem64001987\45\.ThismachineusesmessagepassingasasynchronizationmechanismbetweenbothOSprocessesandI/Ocontrollers.AnI/Oprocessornotifiesthecontrollerthatamessageispending,butitistheresponsibilityofthecontrollertohandlequeues,includingoutoforderprocessinganderrorhandling.c.synchronizationbyinterruptseealsoIBMS/370XAwherepathbusyqueueingishandledbythechannelsubsystem5.asynchronousinstructiontostarttransfera.synchronizationbypollingexampleunknownb.synchronizationbyinterruptIBMS\3701970\16,47\.SIOFstartI/OfastreleaseisusedtoreleasetheCPUafterachannelhasfetcheditsCAWbutbeforethechannelhasdeterminediftheI/Ooperationcanbesuccessfullyinitiated.Aninterruptoccursifthedeviceorpathisbusy.Thedesignersassumedtheseconditionswouldbeinfrequent,butonlatersystemstheinterruptoverheadcanceledoutanyperformancegainfromthefastreleaseofCPU.H.MULTIPROCESSORI/OA.Asymmetricinitiation1.synchronizationbypollingexampleunknown2.synchronizationbyasymmetricinterruptBurroughsB55001964\8,10,28\.ThismachineprovidesuptotwoCPUs,butonlythemasterCPUcaninitiateI/O.AnITIinstructiontotestforpendinginterruptatendofinterrupthandlingpreventsunnecessarycontextswitching.TheI/OchannelsandCPUsarecrossbarredwithmemorymodulesalsotheI/Ochannelsarecrossbarredwithalltheperipherals.IBMS/370MP1974\16,28,47\.ChannelsanddevicesarededicatedtoaparticularCPU.3.synchronizationbysymmetricinterruptUNIVAC1100Model801976\11,12,47\.ThismachineprovidesuptofourCPUs,butI/OmustbeinitiatedbyeitherofthetwoCPUsthatconnecttothestorageinterfaceunitthatcontrolsmemoryaccessfortheI/Odevice.I/OisdirectedtothecacheintheSIUratherthandirectlytomainmemory.I/OinterruptsaremadeavailabletothetwoCPUsinalternationandforalimitedamountoftimeeachifoneCPUdoesntrespondtotheinterruptwithintheavailableperiod,theinterruptispassedontothenextCPUinsequence.B.Symmetricinitiation111.synchronizationbypollingPlesseySystem2501972memorymappedI/Owithcapabilityprotection\19,26,27,33,40\.AdesignphilosophyofreliabilityandsecurityledthedesignerstorejectI/OchannelsinfavorofadditionalCPUsandtorejectinterprocessoranddeviceprocessorinterrupts.Theadvantagesofthisapproachlieinthesimplifiedproblemofcomponentsparing,thepreventionofdisruptionsfromunplannedexternalevents,andtheeaseofhardwareisolationinthecaseofcomponentfailure.DevicedriversobtainI/Orequestsfrommemoryqueuesandpolldeviceregistersuntiltransfersarecomplete.Aninterruptlikesystemisalsoavailableinwhicheachprocessorperiodically100microsec.examinesacommonstatuswordforinterruptlikerequestshowever,variouspapersdifferonitsuseinI/O.seealsoB7700seealsoIBMS/370XAoptionofmaskingoffsubclassesandusingTestSubchannel2.synchronizationbyqueueingIntel4321981alayered,intelligentperipheralsubsystemandobjectorienteddesign\36\.GDPsi.e.CPUscanrequestanI/Ooperationbysendingamessageobjecttoadevicerequestportobject.AnI/OprocessonaninterfaceprocessorIPownsthisportandrespondsbysendingamessagetoanattachedprocessorAPi.e.placingthenecessaryinformationinthelocalmemoryoftheAPandinterruptingtheAP.TheIPhasresponsibilitytoprotectthe432coresystemlogicallyusingcapabilitiesandphysicallyusingseparatebusses,whiletheAPisamoreconventionalmicroprocessore.g.8086andmayusepolling,byteatatimeinterrupts,orDMAcontrollersfortheactualI/Otransfer.ThedevicedriverontheAPformatsareplymessagefromtheI/ObuffersinitslocalmemoryandsendsittotheI/OprocessontheIP,whichthensendsamessageobjecttothecorrespondingdevicereplyportobject.seealsoELXSISystem64003.synchronizationbyasymmetricinterruptRamoWooldridgeRW4001960\8,20,28,46\.MultiplecomputersCPUswithlocalmemoriescanconnectoveracrossbarexchangetospecializedprocessorscalledbuffermemoriesandfromtheretoanyoneofmultipleI/Ocontrollers.Interruptsareavailable,butthepapersareunclearastowhethertheconnecfionbetweenabuffermemoryandI/Ocontrollermustbemaintainedforaninterrupttobesent.CurtinstatesthatconnectionrequestscanonlybemadebythecomputersorbuffermemoriesbutthatacomputercanrequestthatabuffermemorystartI\Ooperationsandthenlatertransferdatafromthebuffermemoryintoitslocalmemory\20\.Enslowindicatesthatacompletesystemwasneverbuilt\28\.Univacll08MP1967\28,47,49\.AnyCPUcaninitiateI/Ooperations,butinterruptsaredirectedtoasingleprespecifiedprocessor.GE6551969,laterrenamedHoneywell6000\28,47\.AnyCPUcaninitiateI/Ooperations,butinterruptsaredirectedtoasinglecontrolprocessorwhichisdeterminedbymanuallysetswitches.4.synchronizationbysymmetricinterruptBurroughsD8251960\2,8,28,53\.AllinterruptsaretransmittedtoeachprocessoranOScontrolledmaskregisterineachprocessordeterminesifitwillrespondtoagiveninterrupt.IBMS/360Model671966\31\.I/OhandlingonthisdualprocessorsystemissimilartoD825.IBMS/370XA1983subchannelperdevice\18,21\.AnyCPUcanstartI/Oonanydevice,andanyCPUcanacceptaninterrupt.Optionally,interruptrequestsfromsubchannelscanbeassignedtooneof12eightmaskableinterruptionsubclasses,andpriorityschemescanbeprogrammedsothatcertainhighpriorityprogramscanbeinterruptedbyonlyasmallnumberofsubclasses.IfallCPUsmaskoffacertainsubclass,theinterruptionstatusisheldpendinginthechannelsystemandcanbeacceptedlaterbyuseofthetestsubchannelinstruction.AtestpendinginterruptioninstructionisalsoavailableandisusedtoavoidanimmediatecontextswitchafteraLPSWisexecutedbytheinterrupthandler.Pathbusyqueueingishandledbythechannelsubsystem.DataGeneralMV/200001985.AnyprocessorcanstartI/Oonanychannel.ChannelseithersendinterruptstoaprocessoridentifiedbyanOSsetregisterinthechanneloraccordingtodevicedirectedinterruptmode,whichusesanOScontrolledtableinmainmemorytomapdevicenumberstoprocessornumbers.SequentBalance1986intelligentinterruptbus\52\.TheSLICbusinterruptstheprocessorcurrentlyrunningtheprogramwithleastpriority.ConcludingRemarksIwouldliketogatherresponsesandcorrectionstothisnewtaxonomyandtothehistoricalinformationinthereviewsection.Anadditionalcategorizationundersynchronizationbyinterruptmightbethedeterminationoftheinterrupthandlerlocation.Forexample,thePDP8hasoneinterruptlocation,whilethePDP11providesasingle,largeinterruptvectortableyieldingthepossibilityofhardwareidentificationofaseparateinterrupthandlerforeachofseveralI/Odevices.Interruptvectortables,asweusethemtoday,apparentlyoriginatedwithIBMStretch,whichalongwiththeHoneywell800providedabaseaddressregisterforthecurrenttable.Thus,differentprocessescouldusedifferenttables.Finally,theRCA601requiredthattheuserspecifytheaddressoftheappropriateinterrupthandleraspartoftheSlartI/Oinstruction\41\.Threeotherissuesmightalsodeserveexplicitcategorizationinallsystems,therecognitionofunsolicitedinpute.g.PDP8versuslockingeachinputunituntilareadisissuede.g.IBMS/360insystemswithcachememory,I/OtocacheUNIVAC1100/80versusI/OtomemoryS/370and,insystemswithvirtualmemory,I/OcontrollerswithvirtualaddressmappingHoneywellDPS8versusI/OcontrollersrequiringpremappedphysicaladdressesS/370.AcknowledgementsIwishtothankRandolphBentsonatColoradoState,HankDietzatPurdue,DanKernatUniv.ofWashington,PhilipKochatDartmouth,JimHaynesatUCSantaCruz,JohnLevineatISC,BarryMargolinatThinkingMachinesCorp.,RobertOlsonatELXSI,DanPiersonatEncore,MarvRubinsteinatISC,DanSiewiorekatCarnegieMellon,JanStubbsatNCR,ChrisThomsonatMyfiasResearch,andSteveWilsonfortheircommentsandsuggestionsonearlierdraftsofthispaper.References\1\G.M.Amdahl,G.A.Blaauw,andF.P.Brooks,Jr.,ArchitectureoftheIBMSystem/360,IBMJ.ResearchandDevelopment8,2April196487101.\2\J.P.Anderson,S.A.Hoffman,J.Shifman,andR.J.Williams,D825AMultipleComputerSystemforCommandandControl,inProc.AFIPSFJCC,1962,pp.8996.\3\M.M.Astrahan,B.Housman,J.F.Jacobs,R.P.Mayer,andW.H.Thomas,LogicalDesignoftheDigitalComputerfortheSAGESystem,IBMJ.ResearchDevelopment1,1,January19577683.\4\T.Atkinson,ArchitectureofSeries60/Level64,HoneywellComp.J.8,2197494106.\5\C.J.Bashe,W.Buchholz,G.V.Hawkins,J.J.Ingram,andN.Rochester,TheArchitectureofIBMsEarlyComputers,IBMJ.ResearchDevelopment25,5September1981363375.\6\C.J.Bashe,L.R.Johnson,J.H.Palmer,andE.W.Pugh,IBMsEarlyComputers.Cambridge,MATheMiT13

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