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49-The Stanford DASH Multiprocessor.pdf

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49-The Stanford DASH Multiprocessor.pdf

THESTANFORDDASHMULTIPROCESSORDANIELLENOSKI,JAMESLAUDON,KOUROSHGHARACHORLOO,WOLFDIETRICHWEBER,ANOOPGUPTA,JOHNHENNESSY,MARKHOROWITZ,ANDMONICASLAMSTANFORDUNIVERSITYDIRECTORYBASEDCACHECOHERENCEGIVESDASHTHEEASEOFUSEOFSHAREDMEMORYARCHITECTURESWHILEMAINTAININGTHESCALABILITYOFMESSAGEPASSINGMACHINESHECOMPUTERSYSTEMSLABORATORYATSTANFORDUNIVERSITYISDEVELOPINGASHAREDMEMORYMULTIPROCESSORCALLEDDASHANABBREVIATIONFORDIRECTORYARCHITECTUREFORSHAREDMEMORYTHEFUNDAMENTALPREMISEBEHINDTHEARCHITECTUREISTHATITISPOSSIBLETOBUILDASCALABLEHIGHPERFORMANCEMACHINEWITHASINGLEADDRESSSPACEANDCOHERENTCACHESTHEDASHARCHITECTUREISSCALABLEINTHATITACHIEVESLINEARORNEARLINEARPERFORMANCEGROWTHASTHENUMBEROFPROCESSORSINCREASESFROMAFEWTOAFEWTHOUSANDTHISPERFORMANCERESULTSFROMDISTRIBUTINGTHEMEMORYAMONGPROCESSINGNODESANDUSINGANETWORKWITHSCALABLEBANDWIDTHTOCONNECTTHENODESTHEARCHITECTUREALLOWSSHAREDDATATOBECACHED,THEREBYSIGNIFICANTLYREDUCINGTHELATENCYOFMEMORYACCESSESANDYIELDINGHIGHERPROCESSORUTILIZATIONANDHIGHEROVERALLPERFORMANCEADISTRIBUTEDDIRECTORYBASEDPROTOCOLPROVIDESCACHECOHERENCEWITHOUTCOMPROMISINGSCALABILITYTHEDASHPROTOTYPESYSTEMISTHEFIRSTOPERATIONALMACHINETOINCLUDEASCALABLECACHECOHERENCEMECHANISMTHEPROTOTYPEINCORPORATESUPTO64HIGHPERFORMANCERISCMICROPROCESSORSTOYIELDPERFORMANCEUPTO16BILLIONINSTRUCTIONSPERSECONDAND600MILLIONSCALARFLOATINGPOINTOPERATIONSPERSECONDTHEDESIGNOFTHEPROTOTYPEHASPROVIDEDDEEPERINSIGHTINTOTHEARCHITECTURALANDIMPLEMENTATIONCHALLENGESTHATARISEINALARGESCALEMACHINEWITHASINGLEADDRESSSPACETHEPROTOTYPEWILLALSOSERVEASAPLATFORMFORSTUDYINGREALAPPLICATIONSANDSOFTWAREONALARGEPARALLELSYSTEMTHISARTICLEBEGINSBYDESCRIBINGTHEOVERALLGOALSFORDASH,THEMAJORFEATURESOFTHEARCHITECTURE,ANDTHEMETHODSFORACHIEVINGSCALABILITYNEXT,WEDESCRIBETHEDIRECTORYBASEDCOHERENCEPROTOCOLINDETAILWETHENPROVIDEANOVERVIEWOFTHEPROTOTYPEMACHINEANDTHECORRESPONDINGSOFTWARESUPPORT,FOLLOWEDBYSOMEMARCH1992PRELIMINARYPERFORMANCENUMBERSTHEARTICLECONCLUDESWITHADISCUSSIONOFRELATEDWORKANDTHECURRENTSTATUSOFTHEDASHHARDWAREANDSOFTWARETHEDASHTEAMMANYGRADUATESTUDENTSANDFACULTVMEMBERSCONTRIBUTEDTOTHEDASHPROJECTTHEPHDSTUDENTSAREDANIELLENOSKIANDJAMESLAUDASHPROJECTOVERVIEWTHEOVERALLGOALOFTHEDASHPROJECTISTOINVESTIGATEHIGHLYPARALLELARCHITECTURESFORTHESEARCHITECTURESTOACHIEVEWIDESPREADUSE,THEYMUSTRUNAVARIETYOFAPPLICATIONSEFFICIENTLYWITHOUTIMPOSINGEXCESSIVEPROGRAMMINGDIFFICULTYTOACHIEVEBOTHHIGHPERFORMANCEANDWIDEAPPLICABILITY,WEBELIEVEAPARALLELARCHITECTUREMUSTPROVIDESCALABILITYTOSUPPORTHUNDREDSTOTHOUSANDSOFPROCESSORSHIGHPERFORMANCEINDIVIDUALPROCESSORS,ANDASINGLESHAREDADDRESSSPACETHEGAPBETWEENTHECOMPUTINGPOWEROFMICROPROCESSORSANDTHATOFTHELARGESTSUPERCOMPUTERSISSHRINKINGWHILETHEPRICEIPERFORMANCEADVANTAGEOFMICROPROCESSORSISINCREASINGTHISCLEARLYPOINTSTOUSINGMICROPROCESSORSASTHECOMPUTEENGINESINAMULTIPROCESSORTHECHALLENGELIESINBUILDINGAMACHINETHATCANSCALEUPITSPERFORMANCEWHILEMAINTAININGTHEINITIALPRICE/PERFORMANCEADVANTAGEOFTHEINDIVIDUALPROCESSORSSCALABILITYALLOWSAPARALLELARCHITECTURETOLEVERAGECOMMODITYMICROPROCESSORSANDSMALLSCALEMULTIPROCESSORSTOBUILDLARGERSCALEMACHINESTHESELARGERMACHINESOFFERSUBSTANTIALLYHIGHERPERFORMANCE,WHICHPROVIDESTHEIMPETUSFORPROGRAMMERSTOPORTTHEIRSEQUENTIALAPPLICATIONSTOPARALLELARCHITECTURESINSTEADOFWAITINGFORTHENEXTHIGHERPERFORMANCEUNIPROCESSORHIGHPERFORMANCEPROCESSORSAREIMPORTANTTOACHIEVEBOTHHIGHTOTALSYSTEMPERFORMANCEANDGENERALAPPLICABILITYUSINGTHEFASTESTMICROPROCESSORSREDUCESTHEIMPACTOFLIMITEDORUNEVENPARALLELISMINHERENTINSOMEAPPLICATIONSITALSOALLOWSAWIDERSETOFAPPLICATIONSTOEXHIBITACCEPTABLEPERFORMANCEWITHLESSEFFORTFROMTHEPROGRAMMERASINGLEADDRESSSPACEENHANCESTHEPROGRAMMABILITYOFAPARALLELMACHINEBYREDUCINGTHEPROBLEMSOFDATAPARTITIONINGANDDYNAMICLOADDISTRIBUTION,TWOOFTHETOUGHESTPROBLEMSINPROGRAMMINGPARALLELMACHINESTHESHAREDADDRESSSPACEALSOIMPROVESSUPPORTFORAUTOMATICALLYPARALLELIZINGCOMPILERS,STANDARDOPERATINGSYSTEMS,MULTIPRODONDASHARCHITECTUREANDHARDWAREDESIGN;KOUROSHGHARACHORLOODASHARCHITECTUREANDCONSISTENCYMODELS;WOLFDIETRICHWEBERDASHSIMULATORANDSCALABLEDIRECTORIES;TRUMANJOEDASHHARDWAREANDPROTOCOLVERIFICATIONTOOLS;LUISSTEVENSOPERATINGSYSTEM;HELENDAVISANDSTEPHENGOLDSCHMIDTTRACEGENERATIONTOOLS,SYNCHRONIZATIONPATTERNS,LOCALITYSTUDIES;TODDMOWRYEVALUATIONOFPREFETCHOPERATIONS;AARONGOLDBERGANDMARGARETMARTONOSIPERFORMANCEDEBUGGINGTOOLS;TOMCHANAKMESHROUTINGCHIPDESIGN;RICHARDSIMONISYNTHETICLOADGENERATORANDDIRECTORYSTUDIES;JOSEPTORRELLASSHARINGPATTERNSINAPPLICATIONS;EDWARDROTHBERG,JASWINDERPALSINGH,ANDLARRYSOULEAPPLICATIONSANDALGORITHMDEVELOPMENTSTAFFRESEARCHENGINEERDAVIDNAKAHIRACONTRIBUTEDTOTHEHARDWAREDESIGNTHEFACULTYASSOCIATEDWITHTHEPROJECTAREANOOPGUPTA,JOHNHENNESSY,MARKHOROWITZ,ANDMONICALAMGRAMMING,ANDINCREMENTALTUNINGOFPARALLELAPPLICATIONSFEATURESTHATMAKEASINGLEADDRESSSPACEMACHINEMUCHEASIERTOUSETHANAMESSAGEPASSINGMACHINECACHINGOFMEMORY,INCLUDINGSHAREDWRITABLEDATA,ALLOWSMULTIPROCESSORSWITHASINGLEADDRESSSPACETOACHIEVEHIGHPERFORMANCETHROUGHREDUCEDMEMORYLATENCYUNFORTUNATELY,CACHINGSHAREDDATAINTRODUCESTHEPROBLEMOFCACHECOHERENCESEETHESIDEBARANDACCOMPANYINGFIGUREWHILEHARDWARESUPPORTFORCACHECOHERENCEHASITSCOSTS,ITALSOOFFERSMANYBENEFITSWITHOUTHARDWARESUPPORT,THERESPONSIBILITYFORCOHERENCEFALLSTOTHEUSERORTHECOMPILEREXPOSINGTHEISSUEOFCOHERENCETOTHEUSERWOULDLEADTOACOMPLEXPROGRAMMINGMODEL,WHEREUSERSMIGHTWELLAVOIDCACHINGTOEASETHEPROGRAMMINGBURDENHANDLINGTHECOHERENCEPROBLEMINTHECOMPILERISATTRACTIVEBUTCURRENTLYCANNOTBEDONEINAWAYTHATISCOMPETITIVEWITHHARDWAREWITHHARDWARESUPPORTEDCACHECOHERENCE,THECOMPILERCANAGGRESSIVELYOPTIMIZEPROGRAMSTOREDUCELATENCYWITHOUTHAVINGTORELYPURELYONACONSERVATIVESTATICDEPENDENCEANALYSISTHEMAJORPROBLEMWITHEXISTINGCACHECOHERENTSHAREDADDRESSMACHINESISTHATTHEYHAVENOTDEMONSTRATEDTHEABILITYTOSCALEEFFECTIVELYBEYONDAFEWHIGHPERFORMANCEPROCESSORSTODATE,ONLYMESSAGEPASSINGMACHINESHAVESHOWNTHISABILITYWEBELIEVETHATUSINGADIRECTORYBASEDCOHERENCEMECHANISMWILLPERMITSINGLEADDRESSSPACEMACHINESTOSCALEASWELLASMESSAGEPASSINGMACHINES,WHILEPROVIDINGAMOREFLEXIBLEANDGENERALPROGRAMMINGMODELDASHSYSTEMORGANIZATIONMOSTEXISTINGMULTIPROCESSORSWITHCACHECOHERENCERELYONSNOOPINGTOMAINTAINCOHERENCEUNFORTUNATELY,SNOOPINGSCHEMESDISTRIBUTETHEINFORMATIONABOUTWHICHPROCESSORSARECACHINGWHICHDATAITEMSAMONGTHECACHESTHUS,STRAIGHTFORWARDSNOOPINGSCHEMESREQUIRETHATALLCACHESSEEEVERYMEMORYREQUESTFROMEVERYPROCESSORTHISINHERENTLYLIMITSTHESCALABILITYOFTHESEMACHINESBECAUSETHECOMMONBUSANDTHEINDIVIDUALPROCESSORCACHESEVENTUALLYSATURATEWITHTODAY’SHIGHPERFORMANCERISCPROCESSORSTHISSATURATIONCANOCCURWITHJUSTAFEWPROCESSORSDIRECTORYSTRUCTURESAVOIDTHESCALABILITYPROBLEMSOFSNOOPYSCHEMESBYREMOVINGTHENEEDTOBROADCASTEVERYMEMORYREQUESTTOALLPROCESSORCACHESTHEDIRECTORYMAINTAINSPOINTERSTOTHEPROCESSORCACHESHOLDINGACOPYOFEACHMEMORYBLOCKONLYTHECACHESWITHCOPIESCANBEAFFECTEDBYANACCESSTOTHEMEMORYBLOCK,ANDONLYTHOSECACHESNEEDBENOTIFIEDOFTHEACCESSTHUS,THEPROCESSORCACHESANDINTERCONNECTWILLNOTSATURATEDUETOCOHERENCEREQUESTSFURTHERMOREDIRECTORYBASEDCOHERENCEISNOTDEPENDENTONANYSPECIFICINTERCONNECTIONNETWORKLIKETHEBUSUSEDBYMOSTSNOOPINGSCHEMESTHESAMESCALABLE,LOWLATENCYNETWORKSSUCHASOMEGANETWORKSORKNARYNCUBESUSEDBYNONCACHECOHERENTAND64COMPUTERCACHECOHERENCECACHECOHERENCEPROBLEMSCANARISEINSHAREDMEMORYMULTIPROCESSORSWHENMORETHANONEPROCESSORCACHEHOLDSACOPYOFADATAITEMAUPONAWRITE,THESECOPIESMUSTBEUPDATEDORINVALIDATEDBMOSTSYSTEMSUSEINVALIDATIONSINCETHISALLOWSTHEWRITINGPROCESSORTOGAINEXCLUSIVEACCESSTOTHECACHELINEANDCOMPLETEFURTHERWRITESINTOTHECACHELINEWITHOUTGENERATINGEXTERNALTRAFFICCTHISFUFTHERCOMPLICATESCOHERENCESINCETHISDIRTYCACHEMUSTRESPONDINSTEADOFMEMORYONSUBSEQUENTACCESSESBYOTHERPROCESSORSDSMALLSCALEMULTIPROCESSORSFREQUENTLYUSEASNOOPYCACHECOHERENCEPROTOCOL,WHICHRELIESONALLCACHESMONITORINGTHECOMMONBUSTHATCONNECTSTHEPROCESSORSTOMEMORYTHISMONITORINGALLOWSCACHESTOINDEPENDENTLYDETERMINEWHENTOINVALIDATECACHELINESB,ANDWHENTOINTERVENEBECAUSETHEYCONTAINTHEMOSTUPTODATECOPYOFAGIVENLOCATIONDSNOOPYSCHEMESDONOTSCALETOALARGENUMBEROFPROCESSORSBECAUSETHECOMMONBUSORINDIVIDUALPROCESSORCACHESEVENTUALLYSATURATE,SINCETHEYMUSTPROCESSEVERYMEMORYREQUESTFROMEVERYPROCESSORONMEMORYREQUESTSBYKEEPINGTRACKOFWHICHCACHESHOLDEACHMEMORYBLOCKASIMPLEDIRECTORYSTRUCTUREFIRSTPROPOSEDBYCENSIERANDFEAUTRIERHASONEDIRECTORYENTRYPERBLOCKOFMEMORYEEACHENTRYCONTAINSONEPRESENCEBITPERPROCESSORCACHEINADDITION,ASTATEBITINDICATESWHETHERTHEBLOCKISUNCACHED,SHAREDINMULTIPLECACHES,ORHELDEXCLUSIVELYBYONECACHETHATIS,WHETHERTHEBLOCKISDIRTYUSINGTHESTATEANDPRESENCEBITS,THEMEMORYCANTELLWHICHCACHESNEEDTOBEINVALIDATEDWHENALOCATIONISWRITTENBLIKEWISE,THEDIRECTORYINDICATESWHETHERMEMORYSCOPYOFTHEBLOCKISUPTODATEORWHICHCACHEHOLDSTHEMOSTRECENTCOPYDIFTHEMEMORYANDDIRECTORYAREPARTITIONEDINTOINDEPENDENTUNITSANDCONNECTEDTOTHEPROCESSORSBYASCALABLEINTERCONNECT,THEMEMORYSYSTEMCANPROVIDESCALABLEMEMORYBANDWIDTHTHEDIRECTORYRELIEVESTHEPROCESSORCACHESFROMSNOOPINGREFERENCES1JARCHIBALDANDJLBAER,CACHECOHERENCEPROTOCOLSEVALUATIONUSINGAMULTIPROCESSORSIMULATIONMODEL,ACMTRANSCOMPUTERSYSTEMS,VOL4,NO4,NOV1986,PP2732982LCENSIERANDPFEAUTRIER,ANEWSOLUTIONTOCOHERENCEPROBLEMSINMULTICACHESYSTEMS,/E€€TRANSCOMPUTERS,VOLC27,NO12,DEC1978,PP1,1121,118STORE3,ACACHECACHE4LOADAERDDATASTATEBITPRESENCEBITSEMESSAGEPASSINGMACHINESCANBEEMPLOYEDTHECONCEPTOFDIRECTORYBASEDCACHECOHERENCEISNOTNEWITWASFIRSTPROPOSEDINTHELATE1970SHOWEVER,THEORIGINALDIRECTORYSTRUCTURESWERENOTSCALABLEBECAUSETHEYUSEDACENTRALIZEDDIRECTORYTHATQUICKLYBECAMEABOTTLENECKTHEDASHARCHITECTUREOVERCOMESTHISLIMITATIONBYPARTITIONINGANDDISTRIBUTINGTHEDIRECTORYANDMAINMEMORY,ANDBYUSINGANEWCOHERENCEPROTOCOLTHATCANSUITABLYEXPLOITDISTRIBUTEDDIRECTORIESINADDITION,DASHPROVIDESSEVERALOTHERMECHANISMSTOMARCH199265REDUCEANDHIDETHELATENCYOFMEMORYOPERATIONSFIGURE1SHOWSDASH’SHIGHLEVELORGANIZATIONTHEARCHITECTURECONSISTSOFANUMBEROFPROCESSINGNODESCONNECTEDTHROUGHDIRECTORYCONTROLLERSTOALOWLATENCYINTERCONNECTIONNETWORKEACHPROCESSINGNODE,ORCLUSTER,CONSISTSOFASMALLNUMBEROFHIGHPERFORMANCEPROCESSORSANDAPORTIONOFTHESHAREDMEMORYINTERCONNECTEDBYABUSMULTIPROCESSINGWITHINTHECLUSTERCANBEVIEWEDEITHERASINCREASINGTHEPOWEROFEACHPROCESSINGNODEORASREDUCINGTHECOSTOFTHEDIRECTORYANDNETWORKINTERFACEBYAMORTIZINGITOVERALARGERNUMBEROFPROCESSORSDISTRIBUTINGMEMORYWITHTHEPROC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