欢迎来到人人文库网! | 帮助中心 人人文库renrendoc.com美如初恋!
人人文库网
首页 人人文库网 > 资源分类 > PDF文档下载

53-Architecture of the Pentium Microprocessor.pdf

  • 资源大小:1,015.14KB        全文页数:11页
  • 资源格式: PDF        下载权限:游客/注册会员/VIP会员    下载费用:5
游客快捷下载 游客一键下载
会员登录下载
下载资源需要5

邮箱/手机号:
您支付成功后,系统会自动为您创建此邮箱/手机号的账号,密码跟您输入的邮箱/手机号一致,以方便您下次登录下载和查看订单。注:支付完成后需要自己下载文件,并不会自动发送文件哦!

支付方式: 微信支付    支付宝   
验证码:   换一换

友情提示
2、本站资源不支持迅雷下载,请使用浏览器直接下载(不支持QQ浏览器)
3、本站资源下载后的文档和图纸-无水印,预览文档经过压缩,下载后原文更清晰   

53-Architecture of the Pentium Microprocessor.pdf

ARCHITECTUREOFTHEPENTIUMMICROPROCESSORTHEPENTIWNCPUISTHELATESTININTEL’SFAMILYOFCOMPATIBLEMICROPROCESSORSITINTEGRATES31MILLIONTRANSISTORSIN08PMBICMOSTECHNOLOGYWEDESCRIBETHETECHNIQUESOFPIPELINING,SUPERSCALAREXECUTION,ANDBRANCHPREDICTIONUSEDINTHEMICROPROCESSOR’SDESIGNHEPENTIUMPROCESSORISINTEL’SNEXTGENERATIONOFCOMPATIBLEMICROPROCESSORSFOLLOWINGTHEPOPULARI486CPUFAMILYTHEDESIGNSTARTEDINEARLY1989WITHTHEPRIMARYGOALOFMAXIMIZINGPERFORMANCEWHILEPRESERVINGSOFTWARECOMPATIBILITYWITHINTHEPRACTICALCONSTRAINTSOFAVAILABLETECHNOLOGYTHEPENTIUMPROCESSORINTEGRATES31MILLIONTRANSISTORSIN08YMBICMOSTECHNOLOGYANDCARRIESTHEINTELTRADEMARKWEDESCRIBETHEARCHITECTUREANDDEVELOPMENTPROCESSEMPLOYEDTOACHIEVETHISGOALDONALDALPERTDRORAVNONHTELCORPORATIONTECHNOLOGYTHECONTINUALADVANCEMENTOFSEMICONDUCTORTECHNOLOGYPROMOTESINNOVATIONINMICROPROCESSORDESIGNHIGHERLEVELSOFINTEGRATION,MADEPOSSIBLEBYREDUCEDFEATURESIZESANDINCREASEDINTERCONNECTIONLAYERS,ENABLEDESIGNERSTODEPLOYADDITIONALHARDWARERESOURCESFORMOREPARALLELCOMPUTATIONANDDEEPERPIPELININGFASTERDEVICESPEEDSLEADTOHIGHERCLOCKRATESANDCONSEQUENTLYTOREQUIREMENTSFORLARGERANDMORESPECIALIZEDONCHIPMEMORYBUFFERSTABLE1NEXTPAGESUMMARIZESTHETECHNOLOGYIMPROVEMENTSASSOCIATEDWITHOURTHREEMOSTRECENTMICROPROCESSORGENERATIONSTHE08YMBICMOSTECHNOLOGYOFTHEPENTIUMMICROPROCESSORENABLES25TIMESTHENUMBEROFTRANSISTORSANDTWICETHECLOCKFREQUENCYOFTHEORIGINALI486CPU,WHICHWASIMPLEMENTEDIN10PMCMOSCOMPATIBIIITYSINCEINTRODUCTIONOFTHE8086MICROPROCESSORIN1978,THEX86ARCHITECTUREHASEVOLVEDTHROUGHSEVERALGENERATIONSOFSUBSTANTIALFUNCTIONALENHANCEMENTSANDTECHNOLOGYIMPROVEMENTS,INCLUDINGTHE80286ANDI386CPUSEACHOFTHESECPUSWASSUPPORTEDBYACORRESPONDINGFLOATINGPOINTUNITTHEI486CPU,’INTRODUCEDIN1989,INTEGRATESTHECOMPLETEFUNCTIONALITYOFANINTEGERPROCESSOR,FLOATINGPOINTUNIT,ANDCACHEMEMORYINTOASINGLECIRCUITTHEX86ARCHITECTUREGREATLYAPPEALEDTOSOFTWAREDEVELOPERSBECAUSEOFITSWIDESPREADAPPLICATIONASTHECENTRALPROCESSOROFIBMCOMPATIBLEPERSONALCOMPUTERSTHESUCCESSOFTHEARCHITECTUREINPCSHASINTURNMADETHEX86POPULARFORCOMMERCIALSERVERAPPLICATIONSASWELLFIGURE1SHOWSSOMEOFTHEWELLKNOWNSOFTWAREENVIRONMENTSTHATAREHOSTEDONTHEARCHITECTURETHECOMMONSOFTWAREENVIRONMENTSALLOWTHEX86ARCHITECTURETOEXERCISESEVERALOPERATINGMODESAPPLICATIONSDEVELOPEDFORDOSUSE16BITREALMODEORVIRTUAL8086MODEANDMSWINDOWSEARLYVERSIONSOFOS/2USE16BITPROTECTEDMODE,ANDAPPLICATIONSFOROTHERPOPULARENVIRONMENTSUSE32BITFLATUNSEGMENTEDMODETHEPENTIUMMICROPROCESSOREMPLOYSGENERALTECHNIQUESFORIMPROVINGPERFORMANCEINALLOPERATINGMODES,ASWELLASCERTAINTECHNIQUESFORIMPROVINGPERFORMANCEINSPECIFICOPERATING02721732/93/06000011030001993IEEEJUNE199311PENTIUMMICROPROCESSORTABLE1TECHNOLOGYFORMICROPROCESSORDEVELOPMENTNOOFFREQUENCYMICROPROCESSORYEARTECHNOLOGYTRANSISTORSMHZ1386CPU198615PMCMOS,275K16TWOLAYERMETALI486CPU19891OPMCMOS,12M33TWOLAYERMETALPENTIUMCPU199308PMBICMOS,31M66THREELAYERMETAL1BITAENERATTON32BITGENERATIONUNIXSVR4SCONETWARE311DOSOSF/1MSWTNDOWSOS121XNEXTSTEP32BITOS/2SOLARISWINDOWSNTIRTALIGENTUNIVEL1980S1991199X1FIGURE1SOFTWAREENVIRONMENTSALLFIGURES,TABLES,ANDPHOTOGRAPHSPUBLLSHEDINTHZSARTICLEARETHEPROPERTYOFINTELCOLPORATIONJII64BITSINTERFACE64BITSPREFETCHBUFFERSPIPELINEDFLOATINGPOINTPIPEIIVPIPEUNITINTEGERINTEGERREGISTERSETMULTIPLIER32BITSIADDERII4DATACACHEI1DIVIDERIFIGURE2PENTIUMPROCESSORBLOCKDIAGRAMMODESWEFOCUSONTHE32BITFLATMODEHERE,SINCETHISISTHEMOSTAPPROPRIATEMODEFORCOMPARISONWITHTHEOTHERHIGHPERFORMANCEMICROPROCESSORSDESCRIBEDATTHEHOTCHIPSIVCONFERENCETHEX86ARCHITECTURESUPPORTSTHEIEEE754STANDARDFORFLOATINGPOINTARITHMETIC’INADDITIONTOREQUIREDOPERATIONSONSINGLEPRECISIONANDDOUBLEPRECISIONFORMATS,THEXS6FLOATINGPOINTARCHITECTUREINCLUDESOPERATIONSON8OBIT,EXTENDEDPRECISIONFORMATANDASETOFBASICTRANSCENDENTALFUNCTIONSPENTIUMCPUDESIGNERSFOUNDNUMEROUSEXCITINGTECHNICALCHALLENGESINDEVELOPINGAMICROARCHITECTURETHATMAINTAINEDCOMPATIBILITYWITHSUCHADIVERSESOFTWAREBASELATERINTHISARTICLEWEPRESENTEXAMPLESOFTECHNIQUESFORSUPPORTINGSELFMODIFYINGCODEANDTHESTACKORIENTED,FLOATINGPOINTREGISTERFILEPERFORMANCEAMICROPROCESSOR’SPERFORMANCEISACOMPLEXFUNCTIONOFMANYPARAMETERSTHATVARYBETWEENAPPLICATIONS,COMPILERS,ANDHARDWARESYSTEMSINDEVELOPINGTHEPENTIUMMICROPROCESSOR,THEDESIGNTEAMADDRESSEDTHESEASPECTSFOREACHOFTHEPOPULARSOFTWAREENVIRONMENTSASARESULT,PENTIUMCPUFEATURESTUNEDCOMPILERSANDCACHEMEMORYWEFOCUSONTHEPERFORMANCEOFSPECBENCHMARKSFORBOTHTHEPENTIUMMICROPROCESSORANDI486CPUINSYSTEMSWITHWELLTUNEDCOMPILERSANDCACHEMEMORYMORESPECIFICALLY,THEPENTIUMCPUACHIEVESROUGHLYTWOTIMESTHESPEEDUPONINTEGERCODEANDUPTOFIVETIMESTHESPEEDUPONFLOATINGPOINTVECTORCODEWHENCOMPAREDWITHANI486CPUOFIDENTICALCLOCKFREQUENCYORGANIZATIONFIGURE2SHOWSTHEOVERALLORGANIZATIONOFTHEPENTIUMMICROPROCESSORTHECOREEXECUTIONUNITSARETWOINTEGERPIPELINESANDAFLOATINGPOINTPIPELINEWITHDEDICATEDADDER,MULTIPLIER,ANDDIVIDERSEPARATEONCHIPINSTRUCTIONCODEANDDATACACHESSUPPLYTHEMEMORYDEMANDSOFTHEEXECUTIONUNITS,WITHABRANCHTARGETBUFFERAUGMENTINGTHEINSTRUCTIONCACHEFORDYNAMICBRANCHPREDICTIONTHEEXTERNALINTERFACEINCLUDESSEPARATEADDRESSAND64BITDATABUSESINTEGERPIPELINETHEPENTIUMPROCESSOR’SINTEGERPIPELINEISSIMILARTOTHATOFTHEI486CPU3THEPIPELINEHASFIVESTAGESSEEFIGURE3WITHTHEFOLLOWINGFUNCTIONSPREFTCCHDURINGTHEPFSTAGETHECPUPREFETCHESCODEFROMTHEINSTRUCTIONCACHEANDALIGNSTHECODETOTHE12IEEEMICROPFD1D2EWBFETCHANDALIGNINSTRUCTIONLDECODEINSTRUCTIONGENERATECONTROLWORDDECODECONTROLWORDGENERATEMEMORYADDRESSCACCESSDATACACHEORCALCULATEALURESULTWRITERESULTIIFIGURE3INTEGERPIPELINEPFD1D2EWBFETCHANDALIGNINSTRUCTIONLDECODEINSTRUCTIONGENERATECONTROLWORDDECODECONTROLWORDIGENERATEMEMORYADDRESSIIACCESSDATACACHEORCALCULATEALURESULTIDECODECONTROLWORDIGENERATEMEMORYADDRESSIACCESSDATACACHEORCALCULATEALURESULTWRITERESULTWRITERESULTUPIPEVPIPEFIGURE4SUPERSCALAREXECUTIONINITIALBYTEOFTHENEXTINSTRUCTIONTOBEDECODEDBECAUSEINSTRUCTIONSAREOFVARIABLELENGTH,THISSTAGEINCLUDESBUFFERSTOHOLDBOTHTHELINECONTAININGTHEINSTRUCTIONBEINGDECODEDANDTHENEXTCONSECUTIVELINEFIRSTDECODEINTHED1STAGETHECPUDECODESTHEINSTRUCTIONTOGENERATEACONTROLWORDASINGLECONTROLWORDEXECUTESINSTRUCTIONSDIRECTLY;MORECOMPLEXINSTRUCTIONSREQUIREMICROCODEDCONTROLSEQUENCINGIND1SECONDDECODEINTHED2STAGETHECPUDECODESTHECONTROLWORDFROMD1FORUSEINTHEESTAGEINADDITION,THECPUGENERATESADDRESSESFORDATAMEMORYREFERENCESEXECUTEINTHEESTAGETHECPUEITHERACCESSESTHEDATACACHEORCALCULATESRESULTSINTHEMUARITHMETICLOGICUNIT,BARRELSHIFTER,OROTHERFUNCTIONALUNITSINTHEDATAPATHWRITEBUCKINTHEWBSTAGETHECPUUPDATESTHEREGISTERSANDFLAGSWITHTHEINSTRUCTION’SRESULTSALLEXCEPTIONALCONDITIONSMUSTBERESOLVEDBEFOREANINSTRUCTIONCANADVANCETOWBCOMPAREDTOTHEINTEGERPIPELINEOFTHEI486CPU,THEPENTIUMMICROPROCESSORINTEGRATESADDITIONALHARDWAREINSEVERALSTAGESTOSPEEDINSTRUCTIONEXECUTIONFOREXAMPLE,THEI486CPUREQUIRESTWOCLOCKSTODECODESEVERALINSTRUCTIONFORMATS,BUTTHEPENTIUMCPUTAKESONECLOCKANDEXECUTESSHIFTANDMULTIPLYINSTRUCTIONSFASTERMORESIGNIFICANTLY,THEPENTIUMPROCESSORSUBSTANTIALLYENHANCESSUPERSCALAREXECUTION,BRANCHPREDICTION,ANDCACHEORGANIZATIONSUPERSCALAREXECUTIONTHEPENTIUMCPUHASASUPERSCALARORGANIZATIONTHATENABLESTWOINSTRUCTIONSTOEXECUTEINPARALLELFIGURE4SHOWSTHATTHERESOURCESFORADDRESSGENERATIONANDMUFUNCTIONSHAVEBEENREPLICATEDININDEPENDENTINTEGERPIPELINES,CALLEDUANDVTHEPIPELINENAMESWERESELECTEDBECAUSEUANDVWERETHEFIRSTTWOCONSECUTIVELETTERSOFTHEALPHABETNEITHEROFWHICHWASTHEINITIALOFAFUNCTIONALUNITINTHEDESIGNPARTITIONINGINTHEPFANDD1STAGESTHECPUCANFETCHANDDECODETWOSIMPLEINSTRUCTIONSINPARALLELANDISSUETHEMTOTHEUANDVPIPELINESADDITIONALLY,FORCOMPLEXINSTRUCTIONSTHECPUIND1CANGENERATEMICROCODESEQUENCESTHATCONTROLBOTHUANDVPIPELINESSEVERALTECHNIQUESAREUSEDTORESOLVEDEPENDENCIESBETWEENINSTRUCTIONSTHATMIGHTBEEXECUTEDINPARALLELMOSTOFTHELOGICISCONTAINEDINTHEINSTRUCTIONISSUEALGORITHMSEEFIGURE5OFD1DECODETWOCONSECUTIVEINSTRUCTIONSI1ANDI2IFTHEFOLLOWINGAREALLTRUEI1ISA”SIMPLE”INSTRUCTIONI2ISA”SIMPLE”INSTRUCTIONI1ISNOTAJUMPINSTRUCTIONDESTINATIONOFI1ZSOURCEOFI2DESTINATIONOFI1JLDESTINATIONOFI2THENISSUE11TOUPIPEANDI2TOVPIPEELSEISSUEI1TOUPIPEFIGURE5INSTRUCTIONISSUEALGORITHMJUNE199313PENTIUMMICROPROCESSORLRBRANCHINSTRUCTIONADDRESSHISTORYBRANCHDESTINATIONADDRESSFIGURE6BRANCHTARGETBUFFERRESOURCEDEPENDENCIESARESOURCEDEPENDENCYOCCURSWHENTWOINSTRUCTIONSREQUIREASINGLEFUNCTIONALUNITORDATAPATHDURINGTHED1STAGE,THECPUONLYISSUESTWOINSTRUCTIONSFORPARALLELEXECUTIONIFBOTHAREFROMACLASSOF“SIMPLE”INSTRUCTIONS,THEREBYELIMINATINGMOSTRESOURCEDEPENDENCIESTHEINSTRUCTIONSMUSTBEDIRECTLYEXECUTEDTHATIS,NOTREQUIREMICROCODESEQUENCINGTHEINSTRUCTIONBEINGISSUEDTOTHEVPIPECANBEANALUOPERATION,MEMORYREFERENCE,ORJUMPTHEINSTRUCTIONBEINGISSUEDTOTHEUPIPECANBEFROMTHESAMECATEGORIESORFROMANADDITIONALSETTHATUSESAFUNCTIONALUNITAVAILABLEONLYINTHEUPIPE,SUCHASTHEBARRELSHIFTERALTHOUGHTHESETOFINSTRUCTIONSIDENTIFIEDAS“SIMPLE”MIGHTSEEMRESTRICTIVE,MORETHAN90PERCENTOFINSTRUCTIONSEXECUTEDINTHEINTEGERSPECBENCHMARKSUITEARESIMPLEDATADEPENDENCIESADATADEPENDENCYOCCURSWHENONEINSTRUCTIONWRITESARESULTTHATISREADORWRITTENBYANOTHERINSTRUCTIONLOGICIND1ENSURESTHATTHESOURCEANDDESTINATIONREGISTERSOFTHEINSTRUCTIONISSUEDTOTHEVPIPEDIFFERFROMTHEDESTINATIONREGISTEROFTHEINSTRUCTIONISSUEDTOTHEUPIPETHISARRANGEMENTELIMINATESREADAFTERWRITERAWANDWRITEAFTERWRITEWAWDEPENDENCIESWRITEAFTERREADWARDEPENDENCIESNEEDNOTBECHECKEDBECAUSEREDDSOCCURINANEARLIERSTAGEOFTHEPIPELINESTHANWRITESTHEDESIGNINCLUDESLOGICTHATENABLESINSTRUCTIONSWITHCERTAINSPECIALTYPESOFDATADEPENDENCYTOBEEXECUTEDINPARALLELFOREXAMPLE,ACONDITIONALBRANCHINSTRUCTIONTHATTESTSTHEFLAGRESULTSCANBEEXECUTEDINPARALLELWITHACOMPAREINSTRUCTIONTHATSETSTHEFLAGSCONTROLDEPENDENCIESACONTROLDEPENDENCYOCCURSWHENTHERESULTOFONEINSTRUCTIONDETERMINESWHETHERANOTHERINSTRUCTIONWILLBEEXECUTEDWHENAJUMPINSTRUCTIONISISSUEDTOTHEUPIPE,THECPUIND1NEVERISSUESANINSTRUCTIONTOTHEVPIPE,THEREBYELIMINATINGCONTROLDEPENDENCIESNOTETHATRESOURCEDEPENDENCIESANDDATADEPENDENCIESBETWEENMEMORYREFERENCESARENOTRESOLVEDIND1DEPENDENTMEMORYREFERENCESCANBEISSUEDTOTHETWOPIPELINES;WEEXPLAINTHEIRRESOLUTIONINTHEDESCRIPTIONOFTHEDATACACHEBRANCHPREDICTIONTHEI486CPUHASASIMPLETECHNIQUEFORHANDLINGBRANCHESWHENABRANCHINSTRUCTIONISEXECUTED,THEPIPELINECONTINUESTOFETCHANDDECODEINSTRUCTIONSALONGTHESEQUENTIALPATHUNTILTHEBRANCHREACHESTHEESTAGEINE,THECPUFETCHESTHEBRANCHDESTINATION,ANDTHEPIPELINERESOLVESW

注意事项

本文(53-Architecture of the Pentium Microprocessor.pdf)为本站会员(baixue100)主动上传,人人文库网仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知人人文库网(发送邮件至[email protected]或直接QQ联系客服),我们立即给予删除!

温馨提示:如果因为网速或其他原因下载失败请重新下载,重复下载不扣分。

关于我们 - 网站声明 - 网站地图 - 资源地图 - 友情链接 - 网站客服客服 - 联系我们

网站客服QQ:2846424093    人人文库上传用户QQ群:460291265   

[email protected] 2016-2018  renrendoc.com 网站版权所有   南天在线技术支持

经营许可证编号:苏ICP备12009002号-5