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56-The Future of Microprocessors.pdf

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56-The Future of Microprocessors.pdf

26SEPTEMBER2005QUEUERANTSFEEDBACKACMQUEUECOMTHEFUTUREOFMICROPROCESSORSKUNLEOLUKOTUNANDLANCEHAMMOND,STANFORDUNIVERSITYQUEUESEPTEMBER200527MOREQUEUEWWWACMQUEUECOMHEPERFORMANCEOFMICROPROCESSORSTHATPOWERMODERNCOMPUTERSHASCONTINUEDTOINCREASEEXPONENTIALLYOVERTHEYEARSFORTWOMAINREASONSFIRST,THETRANSISTORSTHATARETHEHEARTOFTHECIRCUITSINALLPROCESSORSANDMEMORYCHIPSHAVESIMPLYBECOMEFASTEROVERTIMEONACOURSEDESCRIBEDBYMOORE’SLAW,1ANDTHISDIRECTLYAFFECTSTHEPERFORMANCEOFPROCESSORSBUILTWITHTHOSETRANSISTORSMOREOVER,ACTUALPROCESSORPERFORMANCEHASINCREASEDFASTERTHANMOORE’SLAWWOULDPREDICT,2BECAUSEPROCESSORDESIGNERSHAVEBEENABLETOHARNESSTHEINCREASINGNUMBERSOFTRANSISTORSAVAILABLEONMODERNCHIPSTOEXTRACTMOREPARALLELISMFROMSOFTWARETHISISDEPICTEDINfiGURE1FORINTEL’SPROCESSORSANINTERESTINGASPECTOFTHISCONTINUALQUESTFORMOREPARALLELISMISTHATITHASBEENPURSUEDINAWAYTHATHASBEENVIRTUALLYINVISIBLETOSOFTWAREPROGRAMMERSSINCETHEYWEREINVENTEDINTHE1970S,MICROPROCESSORSHAVECONTINUEDTOIMPLEMENTTHECONVENTIONALVONNEUMANNCOMPUTATIONALMODEL,WITHVERYFEWEXCEPTIONSORMODIfiCATIONSTOAPROGRAMMER,EACHCOMPUTERCONSISTSOFASINGLEPROCESSOREXECUTINGASTREAMOFSEQUENTIALINSTRUCTIONSANDCONNECTEDTOAMONOLITHIC“MEMORY”THATHOLDSALLOFTHEPROGRAM’SDATABECAUSETHEECONOMICBENEfiTSOFBACKWARDCOMPATIBILITYWITHEARLIERGENERATIONSOFPROCESSORSARESOSTRONG,HARDWAREDESIGNERSHAVEESSENTIALLYBEENLIMITEDTOENHANCEMENTSTHATHAVEMAINTAINEDTHISABSTRACTIONFORDECADESONTHEMEMORYSIDE,THISHASRESULTEDINPROCESSORSWITHLARGERCACHEMEMORIES,TOKEEPFREQUENTLYACCESSEDPORTIONSOFTHECONCEPTUAL“MEMORY”INSMALL,FASTMEMORIESTHATAREPHYSICALLYCLOSERTOTHEPROCESSOR,ANDLARGEREGISTERfiLESTOHOLDMOREACTIVEDATAVALUESINANCHIPMULTIPROCESSORS’PROMISEOFHUGEPERFORMANCEGAINSISNOWAREALITYMULTIPROCESSORSFOCUS28SEPTEMBER2005QUEUERANTSFEEDBACKACMQUEUECOMEXTREMELYSMALL,FAST,ANDCOMPILERMANAGEDREGIONOF“MEMORY”WITHINPROCESSORS,THISHASRESULTEDINAVARIETYOFMODIfiCATIONSDESIGNEDTOACHIEVEONEOFTWOGOALSINCREASINGTHENUMBEROFINSTRUCTIONSFROMTHEPROCESSOR’SINSTRUCTIONSEQUENCETHATCANBEISSUEDONEVERYCYCLE,ORINCREASINGTHECLOCKFREQUENCYOFTHEPROCESSORFASTERTHANMOORE’SLAWWOULDNORMALLYALLOWPIPELININGOFINDIVIDUALINSTRUCTIONEXECUTIONINTOASEQUENCEOFSTAGESHASALLOWEDDESIGNERSTOINCREASECLOCKRATESASINSTRUCTIONSHAVEBEENSLICEDINTOLARGERNUMBERSOFINCREASINGLYSMALLSTEPS,WHICHAREDESIGNEDTOREDUCETHEAMOUNTOFLOGICTHATNEEDSTOSWITCHDURINGEVERYCLOCKCYCLEINSTRUCTIONSTHATONCETOOKAFEWCYCLESTOEXECUTEINTHE1980SNOWOFTENTAKE20ORMOREINTODAY’SLEADINGEDGEPROCESSORS,ALLOWINGANEARLYPROPORTIONALINCREASEINTHEPOSSIBLECLOCKRATEMEANWHILE,SUPERSCALARPROCESSORSWEREDEVELOPEDTOEXECUTEMULTIPLEINSTRUCTIONSFROMASINGLE,CONVENTIONALINSTRUCTIONSTREAMONEACHCYCLETHESEFUNCTIONBYDYNAMICALLYEXAMININGSETSOFINSTRUCTIONSFROMTHEINSTRUCTIONSTREAMTOfiNDONESCAPABLEOFPARALLELEXECUTIONONEACHCYCLE,ANDTHENEXECUTINGTHEM,OFTENOUTOFORDERWITHRESPECTTOTHEORIGINALPROGRAMBOTHTECHNIQUESHAVEflOURISHEDBECAUSETHEYALLOWINSTRUCTIONSTOEXECUTEMOREQUICKLYWHILEMAINTAININGTHEKEYILLUSIONFORPROGRAMMERSTHATALLINSTRUCTIONSAREACTUALLYBEINGEXECUTEDSEQUENTIALLYANDINORDER,INSTEADOFOVERLAPPEDANDOUTOFORDEROFCOURSE,THISILLUSIONISNOTABSOLUTEPERFORMANCECANOFTENBEIMPROVEDIFPROGRAMMERSORCOMPILERSADJUSTTHEIRINSTRUCTIONSCHEDULINGANDDATALAYOUTTOMAPMOREEFfiCIENTLYTOTHEUNDERLYINGPIPELINEDORPARALLELARCHITECTUREANDCACHEMEMORIES,BUTTHEIMPORTANTPOINTISTHATOLDORUNTUNEDCODEWILLSTILLEXECUTECORRECTLYONTHEARCHITECTURE,ALBEITATLESSTHANPEAKSPEEDSUNFORTUNATELY,ITISBECOMINGINCREASINGLYDIFfiCULTFORPROCESSORDESIGNERSTOCONTINUEUSINGTHESETECHNIQUESTOENHANCETHESPEEDOFMODERNPROCESSORSTYPICALINSTRUCTIONSTREAMSHAVEONLYALIMITEDAMOUNTOFUSABLEPARALLELISMAMONGINSTRUCTIONS,3SOSUPERSCALARPROCESSORSTHATCANISSUEMORETHANABOUTFOURINSTRUCTIONSPERCYCLEACHIEVEVERYLITTLEADDITIONALBENEfiTONMOSTAPPLICATIONSFIGURE2SHOWSHOWEFFECTIVEREALINTELPROCESSORSHAVEBEENATEXTRACTINGINSTRUCTIONPARALLELISMOVERTIMETHEREISAflATREGIONBEFOREINSTRUCTIONLEVELPARALLELISMWASPURSUEDINTENSELY,THENASTEEPRISEASPARALLELISMWASUTILIZEDUSEFULLY,FOLLOWEDBYATAPERINGOFFINRECENTYEARSASTHEAVAILABLEPARALLELISMHASBECOMEFULLYEXPLOITEDCOMPLICATINGMATTERSFURTHER,BUILDINGSUPERSCALARPROCESSORCORESTHATCANEXPLOITMORETHANAFEWINSTRUCTIONSPERCYCLEBECOMESVERYEXPENSIVE,BECAUSETHECOMPLEXITYOFALLTHEADDITIONALLOGICREQUIREDTOfiNDPARALLELINSTRUCTIONSDYNAMICALLYISAPPROXIMATELYPROPORTIONALTOTHESQUAREOFTHENUMBEROFINSTRUCTIONSTHATCANBEISSUEDSIMULTANEOUSLYSIMILARLY,PIPELININGPASTABOUT1020STAGESISDIFfiCULTBECAUSEEACHPIPELINESTAGEBECOMESTOOSHORTTOPERFORMEVENAMINIMALAMOUNTOFINTELPERFORMANCEOVERTIMERELATIVEPERFORMANCEYEAR01010010001000010000010000001985198719891991199319951997199920012003FIG1THEFUTUREOFMICROPROCESSORSMULTIPROCESSORSFOCUSQUEUESEPTEMBER200529MOREQUEUEWWWACMQUEUECOMLOGIC,SUCHASADDINGTWOINTEGERSTOGETHER,BEYONDWHICHTHEDESIGNOFTHEPIPELINEISSIGNIfiCANTLYMORECOMPLEXINADDITION,THECIRCUITRYOVERHEADFROMADDINGPIPELINEREGISTERSANDBYPASSPATHMULTIPLEXERSTOTHEEXISTINGLOGICCOMBINESWITHPERFORMANCELOSSESFROMEVENTSTHATCAUSEPIPELINESTATETOBEflUSHED,PRIMARILYBRANCHESTHISOVERWHELMSANYPOTENTIALPERFORMANCEGAINFROMDEEPERPIPELININGAFTERABOUT30STAGESFURTHERADVANCESINBOTHSUPERSC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