关于at89c51单片机的中英翻译

The Introduction of AT 89C51 Description Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry- standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristic The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC: Supply voltage. GND: Ground. Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high- order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below。 RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE- disable bit has no effect if the microcontroller is in external execution mode. PSEN: Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. The spinal receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2: Output form the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide- by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Idle Mode In idle mode, the CPU puts itself to sleep while all the chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On- chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power- down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. AT89C51 的介绍 描述 单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空 调控制系统，汽车发动机和其他一些领域。这些单片机的高速处理速 度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然 而，这些关键应用领域也要求这些单片机高度可靠。强健的测试环境 和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工 具环境保证了高可靠性和低市场风险。AT89C51 是一个低电压，高 性能 CMOS8 位单片机带有 4K 字节的可反复擦写的程序存储器 （PENROM）和 128 字节的存取数据存储器（ RAM） ，这种器件采用 ATMEL 公司的高密度、不容易丢失存储技术生产，并且能够与 MCS-51 系列的单片机兼容。片内含有 8 位中央处理器和闪速存储单 元，有较强的功能的 AT89C51 单片机能够被应用到控制领域中。 功能特性 AT89C51 提供以下的功能标准：4K 字节闪速存储器， 128 字节 随机存取数据存储器，32 个 I/O 口，2 个 16 位定时/ 计数器，1 个 5 向量两级中断结构，1 个串行通信口，片内震荡器和时钟电路。另外， AT89C51 还可以进行静态逻辑操作，并支持两种软件的节电模式。 闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定 时/计数器、串行通信口及中断系统继续工作。掉电方式保存随机存 取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工 作直到下一个复位。 引脚功能说明 VCC：电源电压。 GND：地。 Port 0：P0 是一组 8 位漏极开路型双向 I/O （输入/输出）口， 也即地址/数据总线复用。作为输出口用时，每位能吸收电流的方式 驱动 8 个 TTL 逻辑门电路，对端口写“1”可作为高阻抗输入端用。 在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低 8 位）和数据总线复用，在访问期间激活内部上拉电阻。在 Flash 编 程时，P0 口接受指令字节，而在程序校验时，输出指令字节。校验 时，要求外接上拉电阻。 Port 1：P1 是一个带内部上拉电阻的 8 位双向 I/O（输入/ 输出） 口，P1 的输出缓冲级可驱动（吸收或输出电流）4 个 TTL 逻辑门电 路。对端口写“1” ，通过内部的上拉电阻把端口拉到高电平，此时可 作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被 外部信号拉低时会输出一个电流（IIL） 。Flash 编程和程序校验期间， P1 接受低 8 位地址。 Port 2：P2 是一个带有内部上拉电阻的 8 位双向 I/O（输入/ 输出） 口，P2 的输出缓冲级可驱动（吸收或输出电流）4 个 TTL 逻辑门 电路。对端口写“1” ，通过内部的上拉电阻把端口拉到高电平，此时 可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚 被外部信号拉低时会输出一个电流（IIL） 。在访问外部程序存储器或 16 位四肢的外部数据存储器（例如执行 MOVX DPTR 指令）时， P2 口送出高 8 位地址数据，在访问 8 位地址的外部数据存储器（例 如执行 MOVX RI 指令）时，P2 口线上的内容（也即特殊功能寄 存器（SFR ）区中 R2 寄存器的内容） ，在整个访问期间不改变。 Flash 编程和程序校验时，P2 也接收高位地址和其他控制信号。 Port 3：P3 是一个带有内部上拉电阻的 8 位双向 I/O 口，P3 的输 出缓冲级可驱动（吸收或输出电流）4 个 TTL 逻辑门电路。对端口 写“1” ，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。 作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉 低时会输出一个电流（IIL） 。 P3 口还接收一些用于 Flash （闪速存储器）编程和程序校验的 控制信号。 RST：复位输入。当振荡器工作时，RST 引脚出现两个机器周期 以上高电平将使单片机复位。 ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址 锁存允许）输出脉冲用于锁存地址的低 8 位字节。即使不访问外部 存储器，ALE 仍以时钟振荡频率的 1/6 输出固定的正脉冲信号，因 此它可对外输出时钟或用于定时目的。要注意的是，每当访问外部数 据存储器时将跳过一个 ALE 脉冲。对 Flash 存储器编程期间，该引 脚还用于输入编程脉冲（PROG） 。如有必要，通过对特殊功能寄存器 （SFR ）区中的 8EH 单元 D0 位置设定，可禁止 ALE 操作。该位 置设定后，只有一条 MOVX 和 MOVC 指令 ALE 才会被激活。此 外，该引脚会被微弱拉高，单片机执行外部程序时，应设置 ALE 无 效。 PSEN：程序存储允许输出是外部程序存储器的读选通型号，当 AT89C51 由外部存储器取指令（或数据）时，每个机器周期内 PSEN 被激活两次，即输出两个脉冲。在