北航电子电路设计数字部分实验报告.docx

电子电路设计数字部分实验报告学 院： 姓名：实验一 简单组合逻辑设计实验内容描述一个可综合的数据比较器，比较数据a 、b的大小，若相同，则给出结果1，否则给出结果0。实验仿真结果实验代码主程序module compare(equal,a,b); input7:0 a,b; output equal; assign equal=(ab)?1:0; endmodule测试程序module t; reg7:0 a,b; reg clock,k; wire equal; initial begin a=0; b=0; clock=0; k=0; end always #50 clock = clock; always (posedge clock) begin a0=$random%2; a1=$random%2; a2=$random%2; a3=$random%2; a4=$random%2; a5=$random%2; a6=$random%2; a7=$random%2; b0=$random%2; b1=$random%2; b2=$random%2; b3=$random%2; b4=$random%2; b5=$random%2; b6=$random%2; b7=$random%2; end initial begin #100000 $stop;end compare m(.equal(equal),.a(a),.b(b); endmodule实验二 简单分频时序逻辑电路的设计实验内容用always块和(posedge clk)或(negedge clk)的结构表述一个1/2分频器的可综合模型，观察时序仿真结果。实验仿真结果实验代码主程序module half_clk(reset,clk_in,clk_out); input clk_in,reset; output clk_out; reg clk_out; always(negedge clk_in) begin if(!reset) clk_out=0; else clk_out=clk_out; end endmodule测试程序timescale 1ns/100psdefine clk_cycle 50module top; reg clk,reset; wire clk_out; always #clk_cycle clk=clk; initial begin clk=0; reset=1; #10 reset=0; #110 reset=1; #100000 $stop; end half_clk m0(.reset(reset),.clk_in(clk),.clk_out(clk_out);endmodule实验三 利用条件语句实现计数分频时序电路实验内容利用10MHz的时钟，设计一个单周期形状的周期波形。实验仿真结果实验代码主程序module fdivision(RESET,F10M,out); input F10M,RESET; output out; reg out; reg7:0 i; always (posedge F10M) if(!RESET) begin out=0; i=0; end else if(i=2|i=3) begin out=out; i=i+1; end else if(i=5) i=1; else i=i+1; endmodule测试程序timescale 1ns/100psmodule division_top; reg F10M,RESET; wire out; always #50 F10M=F10M; initial begin RESET=1; F10M=0; #90 RESET=0; #100 RESET=1; #10000 $stop; end fdivision fdivision(.RESET(RESET),.F10M(F10M),.out(out);endmodule实验四 阻塞赋值与非阻塞赋值的区别实验内容比较四种不同的写法，观察阻塞与非阻塞赋值的区别。Blocking：always (posedge clk) begin b=a; c=b; endBlocking1：always (posedge clk) begin c=b;b=a;endBlocking2：always (posedge clk) b=a;always (posedge clk) c=b;non_Blocking：always(posedge clk) begin b=a; c=b; End实验仿真结果实验代码主程序module blocking(clk,a,b,c); output3:0 b,c; input3:0 a; input clk; reg3:0 b,c; always (posedge clk) begin b=a; c=b; endendmodule测试部分timescale 1 ns/100 psinclude ./blocking.vinclude ./blocking1.vinclude ./blocking2.vinclude ./non_blocking.vmodule compareTop; wire3:0b11,c11,b12,c12,b13,c13,b2,c2; reg3:0a; reg clk; initial begin clk=0; forever#50 clk=clk; end initial begin a=4h3; $display(%d,a); #100 a=4h7; $display(%d,a); #100 a=4hf; $display(%d,a); #100 a=4ha; $display(%d,a); #100 a=4h2; $display(%d,a); #100 $stop; end blocking blocking(clk,a,b11,c11); blocking1 blocking1(clk,a,b12,c12); blocking2 blocking2(clk,a,b13,c13); non_blocking non_blocking(clk,a,b2,c2);endmodule实验五 用always块实现较复杂的组合逻辑实验目的运用always块设计一个8路数据选择器。要求：每路输入数据与输出数据均为4位2进制数，当选择开关（至少3位）或输入数据发生变化时，输出数据也相应地变化。实验仿真结果实验代码主程序module alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8); output3:0 out; reg3:0 out; input3:0 a0,a1,a2,a3,a4,a5,a6,a7; input2:0 opcode; always(opcode or a1 or a2 or a3 or a4 or a5 or a6 or a7 or a0) begin case(opcode) 3d0: out=a0; 3d1: out=a1; 3d2: out=a2; 3d3: out=a3; 3d4: out=a4; 3d5: out=a5; 3d6: out=a6; 3d7: out=a7; default:out=4b0000; endcase endendmodule测试程序timescale 1ns/1nsinclude ./main5.vmodule alutext; wire3:0 out; reg3:0 a1,a2,a3,a4,a5,a6,a7,a8; reg2:0 opcode; initial begin a1=$random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; repeat(100) begin #100 opcode=$random%8; a1=$random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; end #100 $stop; end alu alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8);endmodule 实验六 在 Verilog HDL中使用函数实验目的设计一个带控制端的逻辑运算电路，分别完成正整数的平方、立方和最大数为5的阶乘运算。实验仿真结果实验代码主程序module tryfunct(clk,n,result1,result2,result3,reset); output31:0result1,result2,result3; input3:0n; input reset,clk; reg31:0result1,result2,result3; always(posedge clk) begin if(!reset) begin result1=0; result2=0; result3=0; end else begin result1=fun1(n); result2=fun2(n); result3=fun3(n); end end function31:0fun1; input3:0operand; fun1=operand*operand; endfunction function31:0fun2; input3:0operand; begin fun2=operand*operand; fun2=operand*fun2; end endfunction function31:0fun3; input3:0operand; reg3:0index; begin fun3=1; if(operand11) for(index=2;index=operand;index=index+1) fun3=index*fun3; else for(index=2;index=10;index=index+1) fun3=index*fun3; end endfunction endmodule测试程序include./main6.vtimescale 1ns/100psmodule tryfunctTop; reg3:0 n,i; reg reset,clk; wire31:0result1,result2,result3; initial begin clk=0; n=0; reset=1; #100 reset=0; #100 reset=1; for(i=0;iy) begin tmp=x; x=y; y=tmp; end endtaskendmodule测试部分1timescale 1ns/100psinclude main7.vmodule task_Top; reg7:0a,b,c,d; wire7:0ra,rb,rc,rd; initial begin a=0;b=0;c=0;d=0; repeat(50) begin #100 a=$random%255; b=$random%255; c=$random%255; d=$random%255; end #100 $stop; end rank rank(.ra(ra),.rb(rb),.rc(rc),.rd(rd),.a(a),.b(b),.c(c),.d(d); endmodule主程序2module rank(a,rst,clk,ra,rb,rc,rd); output7:0ra,rb,rc,rd; input7:0a; input clk,rst; reg7:0ra,rb,rc,rd; reg7:0va,vb,vc,vd; reg3:0i; always(posedge clk or negedge clk) begin if(!rst) begin va=0; vb=0; vc=0; vd=0; i=0; end else begin if(iy) begin tmp=x; x=y; y=tmp; end endtask endmodule测试部分2timescale 1ns/100psinclude main7_other.vmodule task_Top; reg7:0a; wire7:0ra,rb,rc,rd; reg clk,rst; initial begin a=0; rst=0; clk=0; #50 rst=1; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 $stop; end always #100 clk=clk; rank rank(.a(a),.rst(rst),.clk(clk),.ra(ra),.rb(rb),.rc(rc),.rd(rd); endmodule实验八 利用有限状态机进行时序逻辑的设计实验目的设计一个串行数据检测器。要求连续四个或四个以上为1 时输出1，其他输入情况下为0.实验仿真结果实验代码主程序module seqdet(x,z,clk,rst,state); input x,clk,rst; output z; output2:0 state; reg2:0 state; wire z; parameter IDLE=d0,A=d1,B=d2,C=d3,D=d4; assign z=(state=D&x=1)?1:0; always(posedge clk) if(!rst) begin state=IDLE; end else casex(state) IDLE: if(x=1) begin state=A; end A: if(x=1) begin state=B; end else begin state=IDLE; end B: if(x=1) begin state=C; end else begin state=IDLE; end C: if(x=1) begin state=D; end else begin state=IDLE; end D: if(x=1) begin state=D; end else begin state=IDLE; end default:state=IDLE; endcase endmodule 测试代码include main8.vmodule seqdet_Top; reg clk,rst; reg23:0 data; wire2:0 state; wire z,x; assign x=data23; always #10 clk=clk; always(posedge clk) data=data22:0,data23; initial begin clk=0; rst=1; #2 rst=0; #30 rst=1; data=b1001_1111_0111_1110; #500 $stop; end seqdet m(x,z,clk,rst,state);endmodule实验九 楼梯灯实验目的楼下到楼上依次有3个感应灯：灯1、灯2、灯3。当行人上下楼梯时，各个灯感应到后自动点亮，若在8s内感应信号消失，则点亮8s，若感应信号存在时间超过8s，则感应信号消失4s后灯自动关闭。任务1：做出如上逻辑电路设计并仿真；任务2：考虑去抖情况，对于感应信号到达存在毛刺(小于0.5s)，设计合适逻辑并剔出。任务3：若为节约能源，下一个灯点亮的同时将自动关闭上一个灯，做出如上逻辑设计并仿真（仅考虑一个人的情况）实验仿真结果实验代码主程序module light_All(clk10,rst,switch,light); input clk10,rst; input2:0switch; output2:0light; reg2:0state1,state2,state3; reg7:0count1,count2,count3; reg2:0count_1,count_2,count_3; reg2:0light; parameter state1_start=3b000,state2_start=3b000,state3_start=3b000, state1_work=3b001,state2_work=3b001,state3_work=3b001, state1_up=3b010,state2_up=3b010,state3_up=3b010, state1_down=3b011,state2_down=3b011,state3_down=3b011, state1_other=3b100,state2_other=3b100,state3_other=3b100; always(posedge clk10) if(!rst) begin state1=state1_start; count1=8b0; count_1=3b0; end else if(switch0=b1&count_14) count_1=count_1+1; else case(state1) state1_start: if(switch0=b1) begin state1=state1_up; count1=78; end else begin state1=state1_start; light00) begin count1=count1-1; if(switch0=b0&(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else if(switch0=b0) begin state1=state1_down; end else begin state1=state1_other; count1=39; end state1_other: if(switch0=b1) state10) begin count1=count1-1; if(switch0=b0&(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else state1=state1_down; state1_down: begin light0=b0; count_1=3b0; state1=state1_start; end state1_up: begin light0=b1; state1=state1_work; end default: state1=state1_start; endcase always(posedge clk10) if(!rst) begin state2=state2_start; count2=8b0; count_2=3b0; end else if(switch1=b1&count_24) count_2=count_2+1; else case(state2) state2_start: if(switch1=b1) begin state2=state2_up; count2=78; end else begin state2=state2_start; light10) begin count2=count2-1; if(switch1=b0&(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else if(switch1=b0) begin state2=state2_down; end else begin state2=state2_other; count2=39; end state2_other: if(switch1=b1) state20) begin count2=count2-1; if(switch1=b0&(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else state2=state2_down; state2_down: begin light1=b0; count_2=3b0; state2=state2_start; end state2_up: begin light1=b1; state2=state2_work; end default: state2=state2_start; endcase always(posedge clk10) if(!rst) begin state3=state3_start; count3=8b0; count_3=3b0; end else if(switch2=b1&count_34) count_3=count_3+1; else case(state3) state3_start: if(switch2=b1) begin state3=state3_up; count3=78; end else begin state3=state3_start; light20) begin count3=count3-1; if(switch2=b0&(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down; end end else if(switch2=b0) begin state3=state3_down; end else begin state3=state3_other; count3=39; end state3_other: if(switch2=b1) state30) begin count3=count3-1; if(switch2=b0&(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down; end end else state3=state3_down; state3_down: begin light2=b0; count_3=3b0; state3=state3_start; end state3_up: begin light2=b1; state3=state3_work; end default: state3=state3_start; endcase endmodule测试程序timescale 100ns/10nsmodule test_light_All;reg clk10,rst;reg2:0 up,down;wire2:0 swh;wire2:0 li