eda课程设计VHDL语言数字时钟电子琴来自重庆大学电子信息工程.doc

rjy4600_cnt60_160进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_cnt60_1 isport(clk:in std_logic; en:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0); preset:in std_logic; co:out std_logic);end rjy4600_cnt60_1;architecture rtl of rjy4600_cnt60_1 issignal co_1:std_logic; begin process(clk,preset) begin if preset=0 then bcd1=0000; else if clkevent and clk=1 then if en=1 then if bcd1=1001 then bcd1=0000; else bcd1=bcd1+1; end if; else if bcd1=0000 then bcd1=1001; else bcd1=bcd1-1; end if; end if; end if; end if; end process; process(clk,preset,bcd1) begin if preset=0 then bcd10=0000; co_1=0; else if clk=1 and clkevent then if en=1 then if bcd1=1000 and bcd10=0101 then co_1=1; elsif bcd1=1001 and bcd10=0101 then bcd10=0000; co_1=0; elsif bcd1=1001 then bcd10=bcd10+1; co_1=0; end if; else if bcd1=0001 and bcd10=0000 then co_1=0; elsif bcd1=0000 and bcd10=0000 then bcd10=0101; co_1=1; elsif bcd1=0000 then bcd10=bcd10-1; co_1=0; else co_1=0; end if; end if; end if; end if; end process; co=not co_1; end rtl;rjy4600_cnt24：24进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_cnt24 isport(clk:in std_logic; en:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0); end rjy4600_cnt24;architecture rtl of rjy4600_cnt24 isbegin process(clk) begin if clkevent and clk=1 then if en=1 then if bcd1=1001 then bcd1=0000; elsif bcd1=0011 and bcd10=0010 then bcd1=0000; else bcd1=bcd1+1; end if; else if bcd1=0000 and bcd10=0000 then bcd1=0011; elsif bcd1=0000 then bcd1=1001; else bcd1=bcd1-1; end if; end if; end if; end process; process(clk,bcd1) begin if clk=1 and clkevent then if en=1 then if bcd1=0011 and bcd10=0010 then bcd10=0000; elsif bcd1=1001 then bcd10=bcd10+1; end if; else if bcd1=0000 and bcd10=0000 then bcd10=0010; elsif bcd1=0000 then bcd10=bcd10-1; end if; end if; end if; end process; end rtl; rjy4600_div1000：1000分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_div1000 isport(clk:in std_logic; q:out std_logic);end rjy4600_div1000;architecture rtl of rjy4600_div1000 issignal div:integer:=0; begin process(clk) begin if clkevent and clk=1 then if div=999 then div=0;q=1; else div=div+1;q=0; end if; end if; end process; end rtl; rjy4600_display：动态译码及显示扫描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_display isport(din0:in std_logic_vector(3 downto 0); din1:in std_logic_vector(3 downto 0); din2:in std_logic_vector(3 downto 0); din3:in std_logic_vector(3 downto 0); din4:in std_logic_vector(3 downto 0); din5:in std_logic_vector(3 downto 0); clk:in std_logic; led_sa:out std_logic; led_sb:out std_logic; led_sc:out std_logic; led_a:out std_logic; led_b:out std_logic; led_c:out std_logic; led_d:out std_logic; led_e:out std_logic; led_f:out std_logic; led_g:out std_logic; led_dp:out std_logic);end rjy4600_display;architecture behave of rjy4600_display is signal seg:std_logic_vector(6 downto 0); signal sel:std_logic_vector(2 downto 0); signal num:std_logic_vector(3 downto 0); signal s:std_logic_vector(2 downto 0);begin led_sa=sel(0); led_sb=sel(1); led_sc=sel(2); led_a=seg(0); led_b=seg(1); led_c=seg(2); led_d=seg(3); led_e=seg(4); led_f=seg(5); led_g=seg(6);process(clk)beginif clkevent and clk=1 then if s=101 then s=000; else s=s+1; end if;end if;end process;process(s,din0,din1,din2,din3,din4,din5)begin if s=000 then sel=000; num=din0; led_dp=0; elsif s=001 then sel=001; num=din1; led_dp=0; elsif s=010 then sel=010; num=din2; led_dp=0; elsif s=011 then sel=011; num=din3; led_dp=0; elsif s=100 then sel=100; num=din4; led_dp=0; elsif s=101 then sel=101; num=din5; led_dp=0; else sel=XXX; num=XXXX; led_dp=0; end if;end process;seg=0111111when num=0 else 0000110when num=1 else 1011011when num=2 else 1001111when num=3 else 1100110when num=4 else 1101101when num=5 else 1111101when num=6 else 0000111when num=7 else 1111111when num=8 else 1101111when num=9 else 1110111when num=10 else 1111100when num=11 else 0111001when num=12 else 1011110when num=13 else 1111001when num=14 else 0000000when num=15 else -1110001 0000000;end behave; rjy4600_keyin：按键输入模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_keyin isport(tm_ch:in std_logic; ch_h:in std_logic; ch_m:in std_logic; ch_s:in std_logic; clk_1:in std_logic; clk:in std_logic; a_d:in std_logic; co_60_1:in std_logic; co_60_2:in std_logic; o_q1:out std_logic; o_q2:out std_logic; o_q3:out std_logic; o_en:out std_logic; reset:out std_logic );end rjy4600_keyin;architecture rtl of rjy4600_keyin isbeginprocess(clk,tm_ch,clk_1,co_60_2,co_60_1)beginif clkevent and clk=1 then if tm_ch=1 then o_en=1;o_q3=clk_1;o_q2=co_60_2;o_q1=co_60_1; reset=1;-? else o_q1=ch_h;o_q2=ch_m;reset= ch_s;o_q3=0; if a_d=1 then o_en=1; else o_en0010) or (chh=0010) then if ch2 then ch_1=ch+8; else chh_1=chh-1;ch_1=ch-2;-ch_1=ch-1;-d_24=0; end if; elsif chh=0000 and ch=0000 then chh_1=0001;ch_1=0010; else chh_1=chh;ch_1=ch; end if; else chh_1=chh;ch_1=ch; end if; end if;end process;end rtl;rjy4600_shan：闪烁模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_shan isport(clk_5:in std_logic; clk:in std_logic; s:in std_logic; xx:in std_logic_vector(3 downto 0); x:in std_logic_vector(3 downto 0); qq:out std_logic_vector(3 downto 0); q:out std_logic_vector(3 downto 0);end rjy4600_shan;architecture rtl of rjy4600_shan isbeginprocess(clk,clk_5,xx,x,s)beginif clkevent and clk=1 then if s=0 then if clk_5=1 then qq=1111; q= 1111; else qq=xx;q=x; end if; else qq=xx;q=0101 and ss=0101 and m=1001 and mm=0101 then if jishu20000 then sound=clk_1K; else sound=0; end if; if jishu=49999 then jishu=0; else jishu=jishu+1; end if; elsif s=0000 and ss=0000 and m=0000 and mm=0000 then if jishu20000 then sound=clk_2K; else sound=0; end if; if jishu=49999 then jishu=0; else jishu1=jishu1+1; end if; else sound=0; end if;end if; end process;end rtl;rjy4600_naozhong：闹钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_naozhong isport(clk50_1000:in std_logic; naoz:in std_logic; hh:in std_logic_vector(3 downto 0); h:in std_logic_vector(3 downto 0); mm:in std_logic_vector(3 downto 0); m:in std_logic_vector(3 downto 0); ss:in std_logic_vector(3 downto 0); s:in std_logic_vector(3 downto 0); sound:out std_logic);end rjy4600_naozhong;architecture rtl of rjy4600_naozhong issignal nz:std_logic:=0;signal chh:std_logic_vector(3 downto 0);signal ch:std_logic_vector(3 downto 0);signal cmm:std_logic_vector(3 downto 0);signal cm:std_logic_vector(3 downto 0);signal css:std_logic_vector(3 downto 0);signal cs:std_logic_vector(3 downto 0);beginprocess(clk50_1000)begin if clk50_1000event and clk50_1000=0 then if naoz=0 then chh=hh;ch=h;cmm=mm;cm=m;css=ss;cs=s; else if chh=hh and ch=h and cmm=mm and cm=m and css=ss then -and cs=s sound=1; else sound=0; end if; end if; end if;end process;end rtl; rjy4600_nzsound：闹钟响铃library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_nzsound isport(clk50_1000:in std_logic; clk_1K:in std_logic; clk_2K:in std_logic; -clk_1:in std_logic; naozhong_snd:in std_logic; sound:out std_logic);end rjy4600_nzsound;architecture rtl of rjy4600_nzsound issignal jishu:integer range 0 to 50000;signal jishu1:integer range 0 to 50000;signal didi:integer range 0 to 15:=0;beginprocess(clk50_1000)begin if clk50_1000event and clk50_1000=0 then if naozhong_snd=1 then if didi=0 or didi=2 or didi=4 or didi=6 or didi=8 or didi=10 or didi=12 or didi=14 then if jishu20000 then sound=clk_1K; else sound=0; end if; if jishu=49999 then jishu=0;didi=didi+1; else jishu=jishu+1; end if; elsif didi=1 or didi=3 or didi=5 or didi=7 or didi=9 or didi=11 or didi=13 then if jishu120000 then sound=clk_2K; else sound=0; end if; if jishu1=49999 then jishu1=0;didi=didi+1; else jishu1=jishu1+1; end if; else didi=0; sound=0; end if; else sound=0; end if;end if; end process;end rtl;rjy4600_PS2_K：ps2键盘串并行转换library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_PS2_K is Port ( sysclk: in std_logic; ps2clk: in std_logic; ps2data: in std_logic; reset: in std_logic; led: out std_logic_vector(7 downto 0); end rjy4600_PS2_K; architecture behav of rjy4600_PS2_K is signal ps2clk_r : std_logic_vector(2 downto 0); signal ps2clkfall : std_logic; signal q : std_logic_vector(11 downto 0); signal ps2serialdata : std_logic_vector(10 downto 0) ; beginprocess(sysclk,reset) begin if reset=0 then ps2clk_r = 000; elsif rising_edge(sysclk) then ps2clk_r(2) = ps2clk_r(1); ps2clk_r(1) = ps2clk_r(0); ps2clk_r(0) = ps2clk; end if;end process;ps2clkfall=1 when ps2clk_r=110 else 0; process(sysclk) begin if rising_edge(sysclk) then if reset=0 then q 0); elsif ps2clkfall=1 then if q(0)=0 then q = ps2data & 01111111111; else q = ps2data & q(11 downto 1); end if; end if; end if;end process;process(q)begin if q(0) = 0 then ps2serialdata = q(11 downto 1); led = not ps2serialdata(8 downto 1); else led =11111111; end if;end process;end behav;rjy4600_tone_rom1：音符查表及简谱产生library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_tone_rom1 isport(index:in std_logic_vector(7 downto 0); index1:in std_logic_vector(3 downto 0); c_g:in std_logic; play_elec:in std_logic; code:out std_logic_vector(3 downto 0); high1:out std_logic_vector(3 downto 0); tone:out std_logic_vector(10 downto 0);end rjy4600_tone_rom1;architecture rtl of rjy4600_tone_rom1 issignal index0:integer range 0 to 255;signal tone1:integer range 0 to 16#7ff#;signal code1:integer range 0 to 15;begin tone=conv_std_logic_vector(tone1,11); code=conv_std_logic_vector(code1,4); search:process(index) begin index0tone1=2047;code1=0;high1tone1=137;code1=1;high1tone1=345;code1=2;high1tone1=531;code1=3;high1tone1=616;code1=4;high1tone1=772;code1=5;high1tone1=912;code1=6;high1tone1=1035;code1=7;high1tone1=1092;code1=1;high1tone1=1197;code1=2;high1tone1=1290;code1=3;high1tone1=1332;code1=4;high1tone1=1410;code1=5;high1tone1=1480;code1=6;high1tone1=1542;code1=7;high1tone1=1570;code1=1;high1tone1=1622;code1=2;high1tone1=1669;code1=3;high1null; end case; else case index is when 10000010=tone1=2047;code1=0;high1tone1=773;code1=1;high1tone1=912;