多路波形发生器电子设计自动化vhdl语言实验报告.docx

电子设计自动化多路波形发生器指导老师：刘彪电气工程学院电气1003班杨黎102910942012年10月27日一、 实验题目要求 1、对输入时钟信号进行分频，实现三路互差120 的信号。2、实现输出信号的占空比控制 clk: 输入时钟信号 reset: 同步复位信号（低电平有效） div: 输入分频控制信号(注意：6n分频) ctrl: 占空比控制信号 ctrl=1时, 占空比为1:1 ctrl=2时, 占空比为1:2 ctrl=3时, 占空比为2:1 a,b,c: 三路输出信号二、 设计思路及方案1、多路发生器的基本原理分频器而且是可调的。因此可以先设计多个子程序分别使得信号发生器的产生的占空比分别为1:1,1:2,2:1；因此先设div:integer range 1 to 4;。通过信号赋值（tmp,tmp1,tmp2）赋给输出信号a,b,c. 通过n改变输出频率。定义各个变量。2、当resetb=0时,countq=0；当resetb=1时。给脉冲时先定义分频比如果countq (6*div-1)时countq = countq 否则countq为0。3、当cltr=01时即h:l=1:1时如果countq 3*div时tmp=0;否者tmp=1如果countq (6*div-2)时tmp1= 1;否者 tmp1=0;如果countq (4*div-1)时tmp2= 0;否者 tmp2=1;a等于tmp；b=tmp2；c=tmp3；同理：当cltr=10时即h:l=1:2时 当cltr=11时即h:l=2:1时。其中；公式推导如下：当div=1,cltr=01时 当div=2，cltr=01时 countq6 countq12a：0 0 0 1 1 1； a:0 0 0 0 0 0 1 1 1 1 1 1b：1 1 0 0 0 1； b:1 1 1 1 0 0 0 0 0 0 1 1c：0 1 1 1 0 0； c:0 0 1 1 1 1 1 1 0 0 0 0a：countq3时tmp=0 a；countq6时tmp=0else tmp=1 else tmp=1b：countq4时tmp=1 b：countq10 ，tmp=1 else tmp=0 else tmp=0c:countq3时tmp=0 c: countq7时tmp=0else tmp=1 else tmp=1同理：cltr=10，cltr=11.当cltr=01时if(countq 3*div) then tmp= 0;else tmp=1;if(countq (6*div-2) then tmp1= 1;else tmp1=0;if(countq (4*div-1) then tmp2= 0;else tmp2=1;当cltr=10时if(countq 4*div) then tmp= 0;else tmp=1;if(countq 2*div ) then tmp1= 1;else tmp1=0;if(countq (4*div-1) then tmp2= 0; else tmp2=1;当cltr=11时if(countq 2*div) then tmp= 0;else tmp=1;if(countq (4*div-1) then tmp1= 1;else tmp1=0;if(countq 4*div ) then tmp2= 1;else tmp2=0;将信号tmp 赋给a ; tmp1 赋给b ； tmp2 赋给 c ;三、流程图reset=0? 0 1tmp、tmp1、tmp2=0是否有信号输入tmp=a tmp1=b tmp2=c判定ctrl的值 否 是 1 2 3调用相应的子程序 四、实验程序及其波形 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity fashengq is port ( clk:in std_logic; aclk:out std_logic; bclk:out std_logic; cclk:out std_logic; resetb:in std_logic; div:in std_logic_vector(1 downto 0); ctrl:in std_logic_vector(1 downto 0) );end fangshengq;architecture behave of fangshengq issignal tmp:std_logic; signal tmp1:std_logic; signal tmp2:std_logic; signal cnt0:integer range 0 to 5:=0; signal cnt1:integer range 0 to 11:=0; signal cnt2:integer range 0 to 17:=0; signal cnt3:integer range 0 to 23:=0; begin process(clk,resetb,div,ctrl) begin if clkevent and clk=1 then if resetb=0 then cnt0=0; cnt1=0; cnt2=0; cnt3=0; tmp=0; tmp1=0; tmp2=0; elsif resetb=1 then cnt0=cnt0+1; cnt1=cnt1+1; cnt2=cnt2+1; cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp