中科院_段成华_专用集成电路设计_作业2详解.doc

Assignment 21. Give a descriptive definition for each of the following terms.(1) Starting substrateCrystalline silicon wafers(2) Active regionThe region between saturation and cutoff used for linear amplification(3) LOCOS processShort for LOCal Oxidation of Silicon process, amicrofabricationprocess wheresilicon dioxideis formed in selected areas on a silicon wafer having the Si-SiO2interface at a lower point than the rest of the silicon surface(4) Field oxide layerIt is a thin layer of Silicon dioxide present beneath the polysilicon gate that serves as dielectric for gate oxide capacitance(5) Shallow Trench Isolation (STI)An integrated circuit feature which prevents electrical current leakage between adjacent semiconductor device components(6) Positive resist and negative resistPositive resist: a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble to the photoresist developerNegative resist: a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer(7) SputteringA process whereby atoms are ejected from a solid target material due to bombardment of the target by energetic particles(8) Reactive ion etchingAn etching technology that High-energy ions from the plasma, generated under low pressure (vacuum) by an electromagnetic field, attack the wafer surface and react with it(9) Strong inversion layerSemiconductor surface minority carrier concentration is equal to the majority of the body of the carrier concentration, the potential of the formation of a surface of the semiconductor surface is approximately a constant value, the depletion layer charge and depletion layer thickness maxima state called strong inversion layer(10) Threshold voltage of MOS transistorThe voltage at which there are sufficient electrons in the inversion layer to make a low resistance conducting path between the MOSFET source and drain2. P- type well in a 250nm technology has the doping concentration NA = 1015atoms cm-3. Find the limiting value of depletion-layer width wd and the total charge Qd contained in the depletion region. Use at 300K;解：3. As the value of the drain-source voltage is further increased, the assumption that the channel voltage is larger than the threshold all along the channel ceases to hold. This happens when VGS - V(x) VT. At that point, the induced charge is zero, and the conducting channel disappears or is pinched off. No channel exists in the vicinity of the drain region and the current ID remains constant (or saturates). Please explain why the current can keep constant instead of being zero while the conducting channel has already disappeared?Reference:1 James D. Plummer, et al., “Chapter 2 Modern CMOS Technology,” Silicon VLSI Technology: Fundamentals, Practice and Modeling, Prentice Hall, 2000. (Available at our course website)在VDS较小时，它对ID的影响应从两个角度来分析：一方面VDS增加时，沟道的电场强度增大，ID随着增加；另一方面，随着VDS的增加，沟道的不均匀性增大，即沟道电阻增加，ID应该下降，但是在VDS较小时，沟道的不均匀性不明显，在漏极附近的区域内沟道仍然较宽，即VDS对沟道电阻影响不大，故ID随VDS增加而几乎呈线性地增加。随着VDS的进一步增加，靠近漏极一端的PN结上承受的反向电压增大，这里的耗尽层相应变宽，沟道电阻相应增加，ID随VDS上升的速度趋缓。当VDS增加到VDS=VGS-VT，即VGD=VGS -VDS= VT (夹断电压)时，漏极附近的耗尽层即在A点处合拢，如上图所示，这种状态称为预夹断。预夹断后，漏极电流ID0。因为这时沟道仍然存在，沟道内的电场仍能使多数载流子(电子)作漂移运动，并被强电场拉向漏极。若VDS继续增加，使VDSVGS-VT,即VGDVT时，耗尽层合拢部分会有增加，即自A点向源极方向延伸，如下图，