lect2-mipsexCMOS超大规模集成电路设计课件

,Lecture2:MIPSProcessorExample,2:MIPSProcessorExample,2,Outline,DesignPartitioningMIPSProcessorExampleArchitectureMicroarchitectureLogicDesignCircuitDesignPhysicalDesignFabrication,Packaging,Testing,2:MIPSProcessorExample,3,Activity2,Sketchastickdiagramfora4-inputNORgate,2:MIPSProcessorExample,4,CopingwithComplexity,HowtodesignSystem-on-Chip?Manymillions(evenbillions!)oftransistorsTenstohundredsofengineersStructuredDesignDesignPartitioning,2:MIPSProcessorExample,5,StructuredDesign,Hierarchy:DivideandConquerRecursivelysystemintomodulesRegularityReusemoduleswhereverpossibleEx:StandardcelllibraryModularity:well-formedinterfacesAllowsmodulestobetreatedasblackboxesLocalityPhysicalandtemporal,2:MIPSProcessorExample,6,DesignPartitioning,Architecture:Usersperspective,whatdoesitdo?Instructionset,registersMIPS,x86,Alpha,PIC,ARM,MicroarchitectureSinglecycle,multcycle,pipelined,superscalar?Logic:howarefunctionalblocksconstructedRipplecarry,carrylookahead,carryselectaddersCircuit:howaretransistorsusedComplementaryCMOS,passtransistors,dominoPhysical:chiplayoutDatapaths,memories,randomlogic,2:MIPSProcessorExample,7,GajskiY-Chart,2:MIPSProcessorExample,8,MIPSArchitecture,Example:subsetofMIPSprocessorarchitectureDrawnfromPattersonf-1=-1fn=fn-1+fn-2f=1,1,2,3,5,8,13,2:MIPSProcessorExample,12,Fibonacci(Assembly),1ststatement:n=8Howdowetranslatethistoassembly?,2:MIPSProcessorExample,13,Fibonacci(Binary),1ststatement:addi$3,$0,8Howdowetranslatethistomachinelanguage?Hint:useinstructionencodingsbelow,2:MIPSProcessorExample,14,Fibonacci(Binary),Machinelanguageprogram,2:MIPSProcessorExample,15,MIPSMicroarchitecture,Multicyclemarchitecture(Paterson04,Harris07),2:MIPSProcessorExample,16,MulticycleController,2:MIPSProcessorExample,17,LogicDesign,StartattoplevelHierarchicallydecomposeMIPSintounitsTop-levelinterface,2:MIPSProcessorExample,18,BlockDiagram,2:MIPSProcessorExample,19,HierarchicalDesign,2:MIPSProcessorExample,20,HDLs,HardwareDescriptionLanguagesWidelyusedinlogicdesignVerilogandVHDLDescribehardwareusingcodeDocumentlogicfunctionsSimulatelogicbeforebuildingSynthesizecodeintogatesandlayoutRequiresalibraryofstandardcells,2:MIPSProcessorExample,21,VerilogExample,modulefulladder(inputa,b,c,outputs,cout);sums1(a,b,c,s);carryc1(a,b,c,cout);endmodulemodulecarry(inputa,b,c,outputcout)assigncout=(aendmodule,2:MIPSProcessorExample,22,CircuitDesign,Howshouldlogicbeimplemented?NANDsandNORsvs.ANDsandORs?Fan-inandfan-out?Howwideshouldtransistorsbe?Thesechoicesaffectspeed,area,powerLogicsynthesismakesthesechoicesforyouGoodenoughformanyapplicationsHand-craftedcircuitsarestillbetter,2:MIPSProcessorExample,23,Example:CarryLogic,assigncout=(a,Transistors?GateDelays?,2:MIPSProcessorExample,24,Gate-levelNetlist,modulecarry(inputa,b,c,outputcout)wirex,y,z;andg1(x,a,b);andg2(y,a,c);andg3(z,b,c);org4(cout,x,y,z);endmodule,2:MIPSProcessorExample,25,Transistor-LevelNetlist,modulecarry(inputa,b,c,outputcout)wirei1,i2,i3,i4,cn;tranif1n1(i1,0,a);tranif1n2(i1,0,b);tranif1n3(cn,i1,c);tranif1n4(i2,0,b);tranif1n5(cn,i2,a);tranif0p1(i3,1,a);tranif0p2(i3,1,b);tranif0p3(cn,i3,c);tranif0p4(i4,1,b);tranif0p5(cn,i4,a);tranif1n6(cout,0,cn);tranif0p6(cout,1,cn);endmodule,2:MIPSProcessorExample,26,SPICENetlist,.SUBCKTCARRYABCCOUTVDDGNDMN1I1AGNDGNDNMOSW=1UL=0.18UAD=0.3PAS=0.5PMN2I1BGNDGNDNMOSW=1UL=0.18UAD=0.3PAS=0.5PMN3CNCI1GNDNMOSW=1UL=0.18UAD=0.5PAS=0.5PMN4I2BGNDGNDNMOSW=1UL=0.18UAD=0.15PAS=0.5PMN5CNAI2GNDNMOSW=1UL=0.18UAD=0.5PAS=0.15PMP1I3AVDDVDDPMOSW=2UL=0.18UAD=0.6PAS=1PMP2I3BVDDVDDPMOSW=2UL=0.18UAD=0.6PAS=1PMP3CNCI3VDDPMOSW=2UL=0.18UAD=1PAS=1PMP4I4BVDDVDDPMOSW=2UL=0.18UAD=0.3PAS=1PMP5CNAI4VDDPMOSW=2UL=0.18UAD=1PAS=0.3PMN6COUTCNGNDGNDNMOSW=2UL=0.18UAD=1PAS=1PMP6COUTCNVDDVDDPMOSW=4UL=0.18UAD=2PAS=2PCI1I1GND2FFCI3I3GND3FFCAAGND4FFCBBGND4FFCCCGND2FFCCNCNGND4FFCCOUTCOUTGND2FF.ENDS,2:MIPSProcessorExample,27,PhysicalDesign,FloorplanStandardcellsPlacederateby2xforclass.,2:MIPSProcessorExample,36,DesignVerification,Fabricationisslow&expensiveMOSIS0.6mm:$1000,3months65nm:$3M,1monthDebuggingchipsisveryhardLimitedvisibilityintooperationProvedesignisrightbeforebuilding!LogicsimulationCkt.simulation/formalverificationLayoutvs.schematiccomparisonDesign&electricalrulechecksVerificationis50%ofeffortonmostchips!,2:MIPSProcessorExample,37,Fabrication&Packaging,TapeoutfinallayoutFabrication6,8,12”wafersOptimizedforthroughput,notlatency(10weeks!)CutintoindividualdicePackagingBondgoldwiresfromdieI/Opadstopackage,2:MIPSProcessorExample,38,Testing,TestthatchipoperatesDesignerrorsManufacturingerrorsAsingledustparticleorwaferdefectkillsadieYieldsfrom90%to10%Dependsondiesize,maturityofprocessTesteachpartbeforeshippingtocustomer,2:MIPSProcessorExample,39,Customvs.Synthesis,8-bitImplementations,2:MIPSProcessorExample,40,MIPSR300