(最新整理)FPGA芯片中支持不同io电平标准

1、(完整)fpga芯片中支持不同io电平标准(完整)fpga芯片中支持不同io电平标准 编辑整理：尊敬的读者朋友们：这里是精品文档编辑中心，本文档内容是由我和我的同事精心编辑整理后发布的，发布之前我们对文中内容进行仔细校对，但是难免会有疏漏的地方，但是任然希望（(完整)fpga芯片中支持不同io电平标准）的内容能够给您的工作和学习带来便利。同时也真诚的希望收到您的建议和反馈，这将是我们进步的源泉，前进的动力。本文可编辑可修改，如果觉得对您有帮助请收藏以便随时查阅，最后祝您生活愉快 业绩进步，以下为(完整)fpga芯片中支持不同io电平标准的全部内容。在fpga芯片中支持不同io电平标准 2008

2、-06-06 15:15:39| 分类： fpga and dsp 标签： |字号大中小 订阅 i/o bankingsome of the i/o standards described above require vcco and/or vref voltages。 these voltages are externally supplied and connected to device pins that serve groups of iobs， called banks. consequently， restrictions exist about which i/o standa

3、rds can be combined within a given bank. eight i/o banks result from separating each edge of the fpga into two banks （see figure 3). the pinout tables show the bank affiliation of each i/o (see pinout tables， module 4）。 each bank has multiple vcco pins which must be connected to the same voltage. vo

4、ltage requirements are determined by the output standards in use。in the tq144 and pq208 packages, the eight banks have vcco connected together. thus, only one vcco level is allowed in these packages, although different vref values are allowed in each of the eight banks。within a bank， standards may b

5、e mixed only if they use the same vcco. 在spartan iie的这两种封装中，每一个bank的io电引脚是连在一起的，而参考电平引脚是在不同的bank中是独立的，也就是说在所有bank中只能有一个io电平，每一个bank可以有自己的电平。在同一个bank中，可以支持不同的电平标准，但要求电平标准要相互兼容compatible standards are shown in table 2.gtl and gtl+ appear under all voltages because their opendrain outputs do not depend

6、 on vcco。 note that vcco is required for most output standards and for lvttl，lvcmos， and pci inputs。vcco compatible standards 3。3v pci， lvttl， sstl3 i， sstl3 ii， ctt， agp, lvpecl， gtl， gtl+ 2。5v sstl2 i, sstl2 ii, lvcmos2， lvds， bus lvds， gtl， gtl+ 1。8v lvcmos18, gtl, gtl+ 1.5v hstl i, hstl iii， hst

7、l iv， gtl， gtl+ some input standards require a usersupplied threshold voltage, vref. in this case， certain user-i/o pins are automatically configured as inputs for the vref voltage. aboutone in six of the i/o pins in the bank assume this role. vref pins within a bank are interconnected internally an

8、d consequently only one vref voltage can be used withineach bank。 all vref pins in the bank， however， must be connected to the external voltage source for correct operation。in a bank， inputs requiring vref can be mixed with thosethat do not but only one vref voltage may be used within a bank。 the vc

9、co and vref pins for each bank appear in the device pinout tables. within a given package， the number of vref and vcco pins can vary depending on the size of device. in larger devices， more i/o pins convert to vref pins。 since these are always a superset of the vref pins used for smaller devices， it

10、 ispossible to design a pcb that permits migration to a larger device. all vref pins for the largest device anticipated must be connected to the vref voltage, and not used for i/o。不同bank可以用不同的io电压，可以用不同的io标准。同一bank中只能用相同电压io标准。（不太贴切）i/o 电平标准：gtl+： vref= 1。0vhstl class i： vref= 0.75vhstl class ii: vr

11、ef= 0。75vhstl class iii: vref= 0。9vhstl class iv： vref= 0.9vsstl2 class i： vref= 1.25vsstl2 class ii: vref= 1.25vsstl3 class i: vref= 1.5vsstl3 class ii: vref= 1。5vinput output board ref. input source term。 volt. volt。 volt. volt. i/o standard （vref) （vcco） (vcco) (vtt） lvttl (2-24 ma) n/a 3。3 3。3 n

12、/a lvcmos2 n/a 2.5 2.5 n/a lvcmos18 n/a 1.8 1。8 n/a pci （3v， 33 mhz/66 mhz）n/a 3.3 3。3 n/a gtl 0.8 n/a n/a 1。2 gtl+ 1.0 n/a n/a 1.5 hstl class i 0.75 n/a 1.5 0。75 hstl class iii 0。9 n/a 1.5 1.5 hstl class iv 0.9 n/a 1。5 1.5 sstl3 class i and ii 1。5 n/a 3。3 1.5 sstl2 class i and ii 1。25 n/a 2。5 1.25

13、ctt 1.5 n/a 3.3 1.5 agp 1。32 n/a 3.3 n/a lvds， bus lvds n/a n/a 2.5 n/a lvpecl n/a n/a 3.3 n/a i/o standard （vref) （vcco） (vcco） (vtt) lvttl （224 ma) n/a 3.3 3.3 n/a lvcmos2 n/a 2。5 2.5 n/a lvcmos18 n/a 1.8 1.8 n/a pci (3v， n/a 3。3 3.3 n/a 33mhz/66 mhz) gtl 0。8 n/a n/a 1.2 gtl+ 1。0 n/a n/a 1。5 hstl

14、class i 0。75 n/a 1。5 0.75 hstl class iii 0。9 n/a 1.5 1.5 hstl class iv 0。9 n/a 1。5 1。5 sstl3 class i and ii 1。5 n/a 3。3 1。5 sstl2 class i and ii 1.25 n/a 2.5 1。25 ctt 1。5 n/a 3。3 1.5 agp 1.32 n/a 3.3 n/a lvds， bus lvds n/a n/a 2。5 n/a lvpecl n/a n/a 3。3 n/a xilinx fgpa spartan iie i/o 管脚可以配置多种i/o 标准

15、,当和这些电平信号相连时，需要外接相应的vref 电压。（有些电平标准,具体可看数据手册，如上面spartan iie）所谓的vref，指的是器件io pin的参考电压，对于lvttl,lvcoms2,lvcoms18等信号电平标准来说,是不需要接vref的，但是如果是gtl，stl等电平标准来说，vref是必须的。简而言之，需要或者不需要接vref是由其i/o信号需要还是不需要vref来决定的。如，gtl的偏置电压为0。8v,那么vref就必须接0。8v电压。这个电压是给接口信号提供的参考电压，跟fpga的内核,接口电压等等没有什么关系。the spartan-3e starter kit

16、boards includes a 512 mbit （32m x 16) micron technology ddrsdram （mt46v32m16） with a 16-bit data interface, as shown in figure 131。 all ddrsdram interface pins connect to the fpgas i/o bank 3 on the fpga. i/o bank 3 and theddr sdram are both powered by 2。5v， generated by an ltc3412 regulator from th

17、eboards 5v supply input。 the 1。25v reference voltage, common to the fpga and ddrsdram, is generated using a resistor voltage divider from the 2。5v rail.addressfigure 132 provides the user constraint file （ucf) constraints for the ddr sdramaddress pins， including the i/o pin assignment and the i/o st

18、andard used.datafigure 133 provides the user constraint file (ucf) constraints for the ddr sdram datapins， including the i/o pin assignment and i/o standard used。figure 132: ucf location constraints for ddr sdram address inputsnet ”sd_a12” loc = ”p2” | iostandard = sstl2_i ;net ”sd_a11” loc = ”n5” |

19、 iostandard = sstl2_i ;net ”sd_a10” loc = t2” iostandard = sstl2_i ;net ”sd_a9” loc = n4 iostandard = sstl2_i ；net sd_a8 loc = ”h2” iostandard = sstl2_i ；net ”sd_a7” loc = ”h1 iostandard = sstl2_i ;net sd_a loc = ”h3” | iostandard = sstl2_i ；net ”sd_a5 loc = h4” iostandard = sstl2_i ；net ”sd_a4 loc

20、= f4” iostandard = sstl2_i ;net sd_a3 loc = p1 | iostandard = sstl2_i ;net ”sd_a2 loc = r2” | iostandard = sstl2_i ;net ”sd_a1 loc = r3” | iostandard = sstl2_i ;net sd_a loc = ”h5 iostandard = sstl2_i ；net sd_dq” loc = ”g5 iostandard = sstl2_i ;net ”sd_dq” loc = g6” | iostandard = sstl2_i ;net sd_dq

21、11” loc = f2” iostandard = sstl2_i ;net ”sd_dq10” loc = f1 iostandard = sstl2_i ;net sd_dq9” loc = e1” | iostandard = sstl2_i ；net ”sd_dq8 loc = e2” iostandard = sstl2_i ；net ”sd_dq7 loc = ”m6 | iostandard = sstl2_i ；net ”sd_dq6 loc = ”m5” | iostandard = sstl2_i ；net sd_dq5” loc = m4” iostandard = s

22、stl2_i ；net sd_dq4 loc = ”m3 | iostandard = sstl2_i ；net ”sd_dq loc = l4” iostandard = sstl2_i ；net sd_dq loc = l1 | iostandard = sstl2_i ；net sd_dq0” loc = l2 | iostandard = sstl2_i ;figure 13-4 provides the user constraint file (ucf） constraints for the ddr sdramcontrol pins, including the i/o pin

23、 assignment and the i/o standard used。reserve fpga vref pinsfive pins in i/o bank 3 are dedicated as voltage reference inputs, vref。 these pins cannotbe used for general-purpose i/o in a design。 prohibit the software from using thesewith the constraints provided in figure 13-5。5ifigure 13-4: ucf location constraints for ddr sdram control pinsnet sd_ba0” loc = k5” | iostandard = sstl2_i ;net ”sd_ba loc = k6” | iostandard = sstl2_i ；net ”sd_cas” loc = c2 | iostand