EDA考试题目和答案(共40页)

1、设计实验与考核1、 设计一个带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is port(clk,clk1,en,clr:in std_logic; ledout:out std_logic_vector(6 downto 0); scanout,scanout1,co:out std_logic);end counter;architecture a of counter

2、issignal cnt:std_logic_vector(7 downto 0);signal led:std_logic_vector(6 downto 0);signal scan:std_logic;signal hex:std_logic_vector(3 downto 0);begin process(clk) begin if(clkevent and clk=1)then if en=1then if clr=1then cnt0); else if cnt=00111111then cnt=00000000; co=1; else cnt=cnt+1; co=0; end i

3、f; end if; end if; end if; end process;process(clk1) begin if clk1event and clk1=1then scan=not scan; end if;Scanout=scan;Scanout1=not scan;end process;ledout=not led;hex=cnt(7 downto 4) when scan=1else cnt(3 downto 0);with hex selectled=1111001when0001, 0100100when0010, 0110000when0011, 0011001when

4、0100, 0010010when0101, 0000010when0110, 1111000when0111, 0000000when1000, 0010000when1001, 0001000when1010, 0000011when1011, 1000110when1100, 0100001when1101, 0000110when1110, 0001110when1111, 1000000when others;end a;2、 设计一个带计数使能、同步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logi

5、c_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(clk,clk1,en,clr:in std_logic; co,scanout:out std_logic; ledout:out std_logic_vector(6 downto 0);end counter;architecture rtl of counter is signal cnt:std_logic_vector(7 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:st

6、d_logic; signal hex:std_logic_vector(3 downto 0);begin process(clk,clr) begin if clr=1then cnt0); elsif clkevent and clk=1 then if en=1then if cnt=00001001then cnt=00010000; co=0; elsif cnt=00011001then -注意此处，前面跳过了A到F的计数,所以计数到11001 cnt=00000000; co=1; else cnt=cnt+1; co=0; end if; end if; end if; en

7、d process; process(clk1) begin if clk1event and clk1=1then scan=not scan; end if; end process; ledout=not led; scanout=scan; hex=cnt(7 downto 4) when scan=1else cnt(3 downto 0); with hex select led=1111001when0001, 0100100when0010, 0110000when0011, 0011001when0100, 0010010when0101, 0000010when0110,

8、1111000when0111, 0000000when1000, 0010000when1001, 1000000when0000, 1111111when others;end rtl;3、 设计一个带计数使能、异步复位、同步装载的可逆七位二进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(clk,clks,clr,en,stdl,dir:in std_logic; din:in std_logic_ve

9、ctor(6 downto 0); ledout:out std_logic_vector(6 downto 0); scanout:out std_logic);end counter;architecture a of counter is signal cnt:std_logic_vector(6 downto 0); signal hex:std_logic_vector(3 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic;begin process(clk) begin if(clke

10、vent and clk=1)then if clr=1then cnt0); elsif stdl=0then cnt=din; elsif en=1then if dir=1then cnt=cnt+1; else cnt=cnt-1; end if; end if; end if; end process; process(clks) begin if(clksevent and clks=1)then scan=not scan; end if; end process; scanout=scan; ledout=not led; hex=0&cnt(6 downto 4)when s

11、can=1 else cnt(3 downto 0); with hex select led=1111001when0001, 0100100when0010, 0110000when0011, 0011001when0100, 0010010when0101, 0000010when0110, 1111000when0111, 0000000when1000, 0010000when1001, 0001000when1010, 0000011when1011, 1000110when1100, 0100001when1101, 0000110when1110, 0001110when111

12、1, 1000000when others;end a;4、 设计一个带计数使能、同步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter IS GENERIC (count_value:INTEGER:=9);PORT(clk,clr,en,load,dir:IN STD_LOGIC; data_in:IN INTEGER RANGE 0 TO count_value; ledout:OUT STD

13、_LOGIC_VECTOR(6 DOWNTO 0);END counter;ARCHITECTURE a OF counter IS SIGNAL cnt:INTEGER RANGE 0 TO count_value; SIGNAL led:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN PROCESS(load,clk) BEGIN IF load=1 THEN cnt=data_in; elsif clr=1 THEN cnt=0; ELSIF (clkEVENT AND clk=1)THEN IF en=1 THEN IF dir=1 THEN IF cnt=cou

14、nt_value THEN cnt=0; ELSE cnt=cnt+1; end if; else IF cnt=0 THEN cnt=count_value; else cnt=cnt-1; end if; end if; end if; end if; END PROCESS; ledout=NOT led; WITH cnt SELECT led=1111001WHEN 1, 0100100WHEN 2, 0110000WHEN 3, 0011001WHEN 4, 0010010WHEN 5, 0000010WHEN 6, 1111000WHEN 7, 0000000WHEN 8, 00

15、10000WHEN 9, 1000000WHEN 0, 1111111WHEN others;END a;5、 设计一个具有16分频、8分频、4分频和2分频功能的多用分频器。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div4 ISPORT(clk:IN STD_LOGIC; din:IN STD_LOGIC_VECTOR(3 DOWNTO 0); fout:OUT std_LOGIC);END div4;ARCHITECTURE a OF div4 ISbegin proc

16、ess(clk) variable cnt:std_logic_vector(3 downto 0); begin if(clkevent and clk=1) then if cnt=1111 then cnt:=0000; else cnt:=cnt+1; end if; if din=0000 then fout=cnt(3); elsif din=1000 then fout=cnt(2); elsif din=1100 then fout=cnt(1); elsif din=1110 then fout=cnt(0); else fout=1; end if; end if; end

17、 process;end a;6、 设计一个正负脉宽相等的通用分频器。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div ISGENERIC (num:INTEGER:=2);PORT (clk:IN STD_LOGIC; co:OUT STD_LOGIC);END div;ARCHITECTURE rtl OF div ISBEGIN PROCESS(clk) VARIABLE cnt:STD_LOGIC_VECTOR(num downto 0); BEGIN IF(clk

18、event and clk=1)THEN cnt:=cnt+1; END IF; co=0101)then cnt:=0000; else cnt:=cnt+1; end if; cout=1000)then cnt:=0000; cout=1; else cnt:=cnt+1; cout=1110)then cnt:=0000;cout=1; else cnt:=cnt+1;cout=1111)then cnt:=0000; else cnt:=cnt+1; end if; cout=cnt(3); end if;end if;end process; with en select led=

19、0000000when00, 0001000when01, 0001110when10, 1000000when11, 1111111when others;ledout=led;end dgnfenpin;8、 设计一个M序列发生器，M序列为“11110101”library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xulie isport(clk:in std_logic; fout:out std_logic);end xulie;architecture fashengqi of x

20、ulie issignal cnt:std_logic_vector(2 downto 0);beginprocess(clk)beginif(clkevent AND clk=1)then if(cnt=111)then cnt=000; else cnt=cnt+1; end if;end if;end process;with cnt select fout=1when000, 1when001, 1when010, 1when011, 0when100, 1when101, 0when “110”,1when”111”, 0when others;end fashengqi;9、 设计

21、一个彩灯控制器，彩灯共有16个，每次顺序点亮相邻的四个彩灯，如此循环执行，循环的方向可以控制。答：library ieee;use ieee.std_logic_1164.all;entity caideng isport( rl,clk:in std_logic;ledout:out std_logic_vector(15 downto 0);end caideng;architecture a of caideng issignal led:std_logic_vector(15 downto 0);signal k:std_logic;beginprocess(clk)beginif(c

22、lkevent and clk=1)then if(k=0)then led1,1=1,2=1,3=1,others=0); elsif(rl=1)then led=led(14 downto 0)&led(15); elsif(rl=0)then led=led(0)&led(15 downto 1); end if;end if;ledout=led;end process;end a;10、 设计一个具有左移、右移控制，同步并行装载和串行装载的8位串行移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY shifter1 ISPORT(

23、clk,clr,ser,dir,stld:IN STD_LOGIC;din: IN STD_LOGIC_VECTOR(0 TO 7) ;qh:OUT STD_LOGIC);END shifter1;ARCHITECTURE rt1 OF shifter1 ISSIGNAL reg:STD_LOGIC_VECTOR(0 TO 7);beginprocess(clk,clr)beginif clr=1 thenreg0);elsif clkevent and clk=1then if stld=0then reg=din; else if(dir=0)then reg=reg(1 to 7)&se

24、r;qh=reg(0); else reg=ser®(0 to 6);qh=”0101”and cnt=”1001”)then gree=1;red=”0000”and cnt=”0100”)thengree=0;red=1; end if;count=cnt;end process;ledout=not led;with count selectled=1111001when0001,0100100when0010,0110000when0011,0011001when0100,0010010when0101,0000010when0110,“1111000”when”0111”,“0

25、000000”when”1000”,“0010000”when”1001”,1000000when others;end rtl;12、 设计一个同步复位，异步并行装载的8位串行左移移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;Entity exam13 isPort(clk,clr,ser,stld:in std_logic;Din:in std_logic_vector(0 to 7);Qh:out std_logic);End exam13;Architecture rtl of exam13 isSignal reg:std_logic_v

26、ector(0 to 7);BeginProcess(clk,stld)Begin If stld=1 thenReg=din; Elsif clkevent and clk=1 thenIf clr=1 then Reg=0);Elsif(stld=0)then Reg=reg(1 to 7)&ser;End if; End if;End process;Qh=reg(0);End rtl;13、 有16个开关，编号为0到15，编号0的优先级最高。当某一个拨码开关为1时由共阴极七段数码管显示其编号（可用16进制数显示，亦可用十进制显示）答：LIBRARY IEEE;USE IEEE.STD_

27、LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY bhxs ISPORT(INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0); LEDOUT: out STD_LOGIC_VECTOR(6 DOWNTO 0);END bhxs;ARCHITECTURE RT1 OF bhxs IS SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN process(INPUT) begin LEDOUT=NOT LED; IF(INPUT(0)=1)then LED=1000000; E

28、LSIF(INPUT(1)=1)then LED=1111001; ELSIF(INPUT(2)=1)then LED=0100100; ELSIF(INPUT(3)=1)then LED=0110000; ELSIF(INPUT(4)=1)then LED=0011001; ELSIF(INPUT(5)=1)then LED=0010010; ELSIF(INPUT(6)=1)then LED=0000010; ELSIF(INPUT(7)=1)then LED=1111000; ELSIF(INPUT(8)=1)then LED=0000000; ELSIF(INPUT(9)=1)then

29、 LED=0010000; ELSIF(INPUT(10)=1)then LED=0001000; ELSIF(INPUT(11)=1)then LED=0000011; ELSIF(INPUT(12)=1)then LED=1000110; ELSIF(INPUT(13)=1)then LED=0100001; ELSIF(INPUT(14)=1)then LED=0000110; ELSIF(INPUT(15)=1)then LEDjiashui=0;qidong=1; If water_low=1then next_state=too_low; Elsif water_high=1the

30、n next_state=too_high; Else next_statejiashui=1;qidong=0; If water_low=1then next_state=too_low; Elsif water_high=1then next_state=too_high; Else next_statejiashui=0;qidong=1; If water_low=1then next_state=too_low; Elsif water_high=1then next_state=too_high; Else next_state=just_right; End if; End c

31、ase, End process;Process(clk) Begin If(clkevent and clk=1)then Now_state=next_state; End if; End process;End style;15、 根据真值表设计一位全加器，然后用结构的描述方法设计一个8位加法器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY full_adder ISPORT(a,b,cin:IN STD_LOGIC; s,co:OUT STD_LOGIC);END full_adder;ARCHITECTURE full1 of ful

32、l_adder isSIGNAL comb:STD_LOGIC_VECTOR(2 downto 0);BEGIN comb=a&b&cin;PROCESS(comb)BEGINIF(comb=000)then s=0;co=0;elsif(comb=001)then s=1;co=0;elsif(comb=100)then s=1;co=0;elsif(comb=010)then s=1;co=0;elsif(comb=011)thens=0;co=1;elsif(comb=101)thens=0;co=1;elsif(comb=110)thens=0;co=1;elses=1;co=1;en

33、d if;end process;end full1;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity full_adder8 isport(clk,cin:in std_logic; x,y:in std_logic_vector(7 downto 0); ledout:out std_logic_vector(6 downto 0);scan_out:out std_logic_vector(1 downto o); co:

34、out std_logic);end full_adder8;architecture stru of full_adder8 iscomponent full_adderport(a,b,cin:in std_logic; s,co:out std_logic);end component; signal z:std_logic_vector(6 downto 0);signal sum:std_logic_vector(7 downto 0);signal scan:std_logic_vector(1 downto 0);signal hex:std_logic_vector(3 dow

35、nto 0);signal led:std_logic_vector(6 downto 0);beginuo:full_adder port map(x(0),y(0),cin,sum(0),z(0);u1:full_adder port map(x(1),y(1),z(0),sum(1),z(1);u2:full_adder port map(x(2),y(2),z(1),sum(2),z(2);u3:full_adder port map(x(3),y(3),z(2),sum(3),z(3);u4:full_adder port map(x(4),y(4),z(3),sum(4),z(4)

36、;u5:full_adder port map(x(5),y(5),z(4),sum(5),z(5);u6:full_adder port map(x(6),y(6),z(5),sum(6),z(6);u7:full_adder port map(x(7),y(7),z(6),sum(7),co);scan_out=scan;ledout=not led;process(clk)begin if(clkevent and clk=1)then if scan=”10” then scan=”01”; else scan=”10”; end if; end if;end process;hex=

37、sum(7 downto 4)when scan=”10” else sum(3 downto 0);with hex selectled=”1000000”when”0000”, “1111001”when”0001”, “0100100”when”0010”, “0110000”when”0011”, “0011001”when”0100”, “0010010”when”0101”, “0000010”when”0110”, “1111000”when”0111”, “0000000”when”1000”, “0010000”when”1001”, “0001000”when”1010”,

38、 “0000011”when”1011”, “1000110”when”1100”, “0100001”when”1101”, “0001110”when”1110”, “0001110”when”1111”, “XXXXXXX”when others;End stru;16、 设计6位二进制数到BCD码（8421码）的转换器。结果由共阴极数码管显示。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY trans ISPORT( scanclk:IN STD_LOGIC; shu:IN

39、STD_LOGIC_VECTOR(5 DOWNTO 0); ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer range 0 to 1);END trans;ARCHITECTURE rtl OF trans IS signal yh,yl:integer range 0 to 9; signal scan:integer range 0 to 1; signal led:std_logic_vector(6 downto 0); signal y,hex:integer range 0 to 63;BEGIN y=con

40、v_integer(shu); yh=10 and y=20 and y=30 and y=40 and y=50 and y=60 and y64 else 0; yl=0 and y=10 and y=20 and y=30 and y=40 and y=50 and y=60 and y70 else0; process(scanclk) begin if(scanclkevent and scanclk=1)then if scan=1 then scan=0; else scan=1; end if; end if; end process; with scan select hex

41、=yh when 1, yl when others; ledout=not led; scanout=scan; with hex select led=1111001when 1, 0100100when 2, 0110000when 3, 0011001when 4, 0010010when 5, 0000010when 6, 1111000when 7, 0000000when 8, 0010000when 9, 1000000when 0,“1111001”when others;END rtl; 17、 设计一个跑马灯控制器。一共有8个彩灯，编号为LED0LED7，点亮方式为：先从

42、左往右顺序点亮，然后从右往左，如此循环往复。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY lighten IS PORT( CLK:IN STD_LOGIC; ledout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END lighten;ARCHITECTURE b OF lighten ISSIGNAL cnt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(CLK) BEGIN IF(CLKEVENT AND CLK=1)THEN IF (cnt=1110)THEN cnt=0000; ELS