教程讲稿数电

1、1Digital Logic Design and ApplicationJin YanhuaLecture #16Demultiplexer ComparatorsUESTC, Spring 2012Jin. UESTC2Last TimeThree-State DevicesMultiplexersENSELD0Dn-1Yn sourcesb-bitb-bit MSI - 151, 153, 157Expanding MultiplexersRealize logic functionJin. UESTC32-input multiplexerJin. UESTC44. Demultipl

2、exerRoute the bus data to one of m destinationsMUX SRCASRCBSRCZDMUXBUSDSTADSTBDSTZSRCSELDSTSELDST : destinationSRC : sourceSEL : selectJin. UESTC5ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_L数据输入 SRC EN_LUse 74x139 as a 1-bit, 4-output demultiplexerDSTSEL0DSTSEL1DSTSEL2地址 选择 The enable input is conn

3、ected to the data line.数据输入 SRC EN EN_Lbinary decoder used as demultiplexerComp.Jin. UESTC6Use 74x139 as a 1-bit, 4-output demultiplexerComp.Jin. UESTC76.8 Parity CircuitsOdd-Parity CircuitOutput is 1 if an odd number of its inputs are 1. Even-Parity CircuitOutput is 1 if an even number of its input

4、s are 1. How to know the number of 1 ?A0 A1 An = 1 odd number of 10 even number of 1If output of odd-parity circuit is inverted, we get an even-parity circuit.Jin. UESTC81. Exclusive-OR and Exclusive-NOR GatesXOR and XNOR gates: 2-input, 1-outputAny two signals (inputs or output) of an XOR or XNOR g

5、ate may be complemented without changing the resulting logic function.F=ABABFABFABABFFF=ABF=(AB)F=(AB)= AB= AB= ABJin. UESTC9Gate-level XOR circuitsXYF = XY XYF = XY Use a few transistors?Jin. UESTC10CMOS XOR with transmission gatesABZIF B=1 THEN Z = !A;ELSE Z = A;Jin. UESTC11Cascading n XOR: n+1-in

6、put, 1-output circuitI1I2I3I4INODD Daisy-Chain ConnectionI1I2I3I4IMINODD Tree Structure2. Parity CircuitsfasterJin. UESTC123. The 74x280 9-Bits Parity GeneratorJin. UESTC134. Parity-Cheching ApplicationsTo detect errors in the transmission and storage of data. AEVENODD74x280HIAEVENODD74x280HI发端收端DB0

7、:7DB0:7ERROR发端保证有偶数个1 收端 ODD 有效表示出错 奇数 EVEN Jin. UESTC14Jin. UESTC156.9 ComparatorsComparator: compare two binary words and indicate whether they are equalMagnitude comparator: indicate an arithmetic relationship between the words ( , =, B AB3)LT = EQ GT = ( EQ + GT )或 (A3 = B3) (A2 = B2) (A1B1)或 (A

8、3 = B3)(A2 = B2)(A1 = B1) (A0B0)或 (A3 = B3) (A2B2)A3B3A2B2A1B1A0B0+Jin. UESTC2074x855. Standard MSI Magnitude ComparatorsA0A1A2A3ALTBINAEQBINAGTBINCascading inputs (Low-order) ALTBOUT = (AB高位A高位=B高位 & A低位B低位ABAEQBOUT = (A=B)AEQBINAGTBOUT = (AB) + (A=B)AGTBIN4-bit comparatorJin. UESTC21Expanding comp

9、arators in seriesXD11:0YD11:03:07:411:8XY+5VABIABOA0A3B0B374x85ABIABOA0A3B0B374x85ABIABOA0A3B0B374x85Build a 12-bit comparators using 74x85sLow-order High-orderJin. UESTC22P0P1P2P3P4P5P6P78-bit comparator 74x682Logic diagram P463 Figure 6-82 Q1: How to get the following outputs? active-high: P DIFF Q active-high: P EQ Q active-high: P GE QGELTQ2: How to expand? Have no cascading inputs! active-high: P LE Q active-high: P LT Q P463 Figure 6-81Jin