现代闪存命名规则.doc

Part Number System Change NoticeEffective from August 6, 2007, a more concise part numbering system is utilized byHynix with the intention of managing product line with more consistency.Devices developed after August 2007 and their respective products will be Refer tothe following pages for more details. (/pn_notice.jsp)Part Number with prefix HY - Old Part Number Decoder LinkPart Number with prefix H - New Part Number Decoder LinkH Part Number Last Updated: Dec. 2007NAND Flash PART NUMBERINGH 2 7 X X X X X X X X X - X X (1) HYNIX(1)(2)(3)(4)(5)(6)(7)(8)(9)(10) (11) (12)(13)(14)(15)(15) OPERATION TEMPERATURE(2) PRODUCT FAMILY2 : FlashC: Commercial (070)E: Extended (-2585)M: Mobile (-3085)I(3) PRODUCT MODE7 : NAND FlashB: Industrial (-4085)(14) BAD BLOCK: Included Bad Block(4) POWER SUPPLY(VCC)U: 2.7V3.6VS: 15 Bad Block IncludedP: All Good BlockLS: 2.7V: 1.8V(13) - d“ - ”(5), (6) DENSITY64: 64Mb12: 128Mb(12) PACKAGE MATERIAL25: 256Mb1G: 1Gb4G: 4GbAG: 16GbCG: 64Gb51: 512Mb2G: 2Gb8G: 8GbBG: 32GbDG: 128GbAPLR: Wafer: Lead Free: Leaded: Lead & Halogen Free(11) PACKAGE TYPE(7) ORGANIZATION8: x86: x16(8) NAND CLASSIFICATIONS: SLC + Single Die + Small BlockA: SLC + Double Die + Small BlockB: SLC + Quadruple Die + Small BlockTVSNFXMYUW: TSOP1: WSOP: USOP: LSOP1: FBGA: LGA: WLGA: VLGA: ULGA: WaferFGHJ: SLC + Single Die + Large Block: SLC + Double Die + Large Block: SLC + Quadruple Die + Large Block: SLC + ODP + Large BlockCKD: PGD1 (chip): KGD: PGD2KTUVWY: SLC + DSP + Large Block: MLC + Single Die + Large Block: MLC + Double Die + Large Block: MLC + Quadruple Die + Large Block: MLC + DSP + Large Block: MLC + ODP + Large Block(10) DIE GENERATIONM: 1stA: 2ndB: 3rdC: 4th (9) FUNCTION MODE1: 1 nCE & 1 R/nB; Sequential Row Read Enable2: 1 nCE & 1 R/nB; Sequential Row Read Disable4: 2 nCE & 2 R/nB; Sequential Row Read Enable5: 2 nCE & 2 R/nB; Sequential Row Read DisableD: Dual Interface; Sequential Row Read DisableF: 4 nCE & 4 R/nB ; Sequential Row Read DisableHY Part Number Last Updated: Dec. 2007NAND Flash PART NUMBERINGHY XX X X XX XX X X - X (X) (X) (X) (X)(1)(1) HYNIX MEMORY(2) COMPONENT GROUP27: NAND Flash(3) POWER SUPPLY(VCC)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(13) OPTION(CUSTOMER)Customer InitialOption(12) BAD BLOCKU: 2.7V3.6VBlank: WaferB: Included Bad BlockLS: 2.7V: 1.8VSP: 15 Bad Block: All Good Block(4) CLASSIFICATION(11) OPERATING TEMPERATURESABFGH: SLC + Single Die + S/B: SLC + Double Die + S/B: SLC + Quadruple Die + S/B: SLC + Single Die + L/B: SLC + Double Die + L/B: SLC + Quadruple Die + L/BBlankCEMI: Wafer, Chip: 070: -2585: -3085: -4085KT: SLC + DSP + L/B: MLC + Single Die + L/B(10) PACKAGE MATERIALUVW: MLC + Double Die + L/B: MLC + Quadruple Die + L/B: MLC + DSP + L/BBlankPHR: Normal, Wafer, Chip, KGD: Lead Free: Halogen Free: Lead & Halogen Free(5) BIT ORGANIZATION08: x8(9) PACKAGE TYPE1632: x16: x32TVS: TSOP1: WSOP: USOP(6) DENSITYE: WELP64561G4GAGCGZG: 64Mb: 256Mb: 1Gb: 4Gb: 16Gb: 64Gb: 48Gb28122G8GBGDG: 128Mb: 512Mb: 2Gb: 8Gb: 32Gb: 128GbFBGHUYMW: FBGA(63ball): FBGA(107ball): FBGA(149ball): TBGA: ULGA: VLGA: WLGA: Wafer(7) MODE1: 1 nCE & 1 R/nB; Sequential Row Read Enable2: 1 nCE & 1 R/nB; Sequential Row Read Disable4: 2 nCE & 2 R/nB; Sequential Row Read Enable5: 2 nCE & 2 R/nB; Sequential Row Read Disable6: 1 nCE & 1 R/nB; Sequential Row Read Enable & Auto Read Page 07: 2 nCE & 2 R/nB; Sequential Row Read Enable & Auto Read Page 08: 1 nCE & 1 R/nB; Sequential Row Read Disable & Auto Read Page 09: 2 nCE & 2 R/nB; Sequential Row Read Disable & Auto Read Page 0D: Dual Interface; Sequential Row Read DisableF: 4 nCE & 4 R/nB ;