文献翻译——STM32F103说明

第1页外文文献资料STM32F103instructions1Documentationconventions1.1ListofabbreviationsforregistersThefollowingabbreviationsareusedinregisterdescriptions:1.2GlossaryLow-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween16and32Kbytes.Medium-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween64and128Kbytes.High-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween256and512Kbytes.XL-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween768Kbytesand1Mbyte.ConnectivitylinedevicesareSTM32F105xxandSTM32F107xxmicrocontrollers.Word:dataof32-bitlength.Half-word:dataof16-bitlength.Byte:dataof8-bitlength.1.3PeripheralavailabilityForperipheralavailabilityandnumberacrossallSTM32F10xxxsalestypes,pleaserefertothelow-,medium-,high-andXL-densitySTM32F101xxandSTM32F103xxdatasheets,to第2页thelow-andmedium-densitySTM32F102xxdatasheetsandtotheconnectivitylinedevices,STM32F105xx/STM32F107xx.2Memoryandbusarchitecture2.1SystemarchitectureInlow-,medium-,high-andXL-densitydevices,themainsystemconsistsof:Fourmasters:Cortex-M3coreDCodebus(D-bus)andSystembus(S-bus)GP-DMA1&2(general-purposeDMA)Fourslaves:InternalSRAMInternalFlashmemoryFSMCAHBtoAPBx(APB1orAPB2),whichconnectalltheAPBperipherals2.2MemoryorganizationProgrammemory,datamemory,registersandI/Oportsareorganizedwithinthesamelinear4-Gbyteaddressspace.ThebytesarecodedinmemoryinLittleEndianformat.Thelowestnumberedbyteinawordisconsideredthewordsleastsignificantbyteandthehighestnumberedbytethemostsignificant.Forthedetailedmappingofperipheralregisters,pleaserefertotherelatedchapters.Theaddressablememoryspaceisdividedinto8mainblocks,eachof512MB.Allthememoryareasthatarenotallocatedtoon-chipmemoriesandperipheralsareconsidered“Reserved”).RefertotheMemorymapfigureinthecorrespondingproductDatasheet.第3页Note:WhenbootingfromSRAM,intheapplicationinitializationcode,youhavetorelocatethevectortableinSRAMusingtheNVICexceptiontableandoffsetregister.ForXL-densitydevices,whenbootingfromthemainFlashmemory,youhaveanoptiontobootfromanyoftwomemorybanks.Bydefault,bootfromFlashmemorybank1isselected.YoucanchoosetobootfromFlashmemorybank2byclearingtheBFB2bitintheuseroptionbytes.WhenthisbitisclearedandthebootpinsareinthebootfrommainFlashmemoryconfiguration,thedevicebootsfromsystemmemory,andthebootloaderjumpstoexecutetheuserapplicationprogrammedinFlashmemorybank2.Forfurtherdetails,pleaserefertoAN2606.Note:WhenbootingfromBank2,intheapplicationsinitializationcode,youhavetorelocatethevectortabletotheBank2baseaddress.(0x08080000)usingtheNVICexceptiontableandoffsetregister.EmbeddedbootloaderTheembeddedbootloaderislocatedintheSystemmemory,programmedbySTduringproduction.ItisusedtoreprogramtheFlashmemorywithoneoftheavailableserialinterfaces:Inlow-,medium-andhigh-densitydevicesthebootoaderisactivatedthroughtheUSART1interface.InXL-densitydevicesthebootloaderisactivatedthroughthefollowinginterfaces:USART1orUSART2(remapped).第4页Inconnectivitylinedevicesthebootloadercanbeactivatedthroughoneofthefollowinginterfaces:USART1,USART2(remapped),CAN2(remapped)orUSBOTGFSinDevicemode(DFU:devicefirmwareupgrade).TheUSARTperipheraloperateswiththeinternal8MHzoscillator(HSI).TheCANandUSBOTGFS,however,canonlyfunctionifanexternal8MHz,14.7456MHzor25MHzclock(HSE)ispresent.Note:Forfurtherdetails,pleaserefertoAN2606.3CRCcalculationunitLow-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween16and32Kbytes.Medium-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween64and128Kbytes.High-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween256and512Kbytes.XL-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween768Kbytesand1Mbyte.ConnectivitylinedevicesareSTM32F105xxandSTM32F107xxmicrocontrollers.ThissectionappliestothewholeSTM32F10xxxfamily,unlessotherwisespecified.3.1CRCintroductionTheCRC(cyclicredundancycheck)calculationunitisusedtogetaCRCcodefroma32-bitdatawordandafixedgeneratorpolynomial.Amongotherapplications,CRC-basedtechniquesareusedtoverifydatatransmissionor第5页storageintegrity.InthescopeoftheEN/IEC60335-1standard,theyofferameansofverifyingtheFlashmemoryintegrity.TheCRCcalculationunithelpscomputeasignatureofthesoftwareduringruntime,tobecomparedwithareferencesignaturegeneratedatlinktimeandstoredatagivenmemorylocation.3.2CRCmainfeaturesUsesCRC-32(Ethernet)polynomial:0x4C11DB7X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1Singleinput/output32-bitdataregisterCRCcomputationdonein4AHBclockcycles(HCLK)General-purpose8-bitregister(canbeusedfortemporarystorage)3.3CRCfunctionaldescriptionTheCRCcalculationunitmainlyconsistsofasingle32-bitdataregister,which:isusedasaninputregistertoenternewdataintheCRCcalculator(whenwritingintotheregister)holdstheresultofthepreviousCRCcalculation(whenreadingtheregister)EachwriteoperationintothedataregistercreatesacombinationofthepreviousCRCvalueandthenewone(CRCcomputationisdoneonthewhole32-bitdataword,andnotbyteperbyte).ThewriteoperationisstalleduntiltheendoftheCRCcomputation,thusallowingback-tobackwriteaccessesorconsecutivewriteandreadaccesses.TheCRCcalculatorcanberesettoFFFFFFFFhwiththeRESETcontrolbitintheCRC_CRregister.ThisoperationdoesnotaffectthecontentsoftheCRC_IDRregister.3.4CRCregistersTheCRCcalculationunitcontainstwodataregistersandacontrol第6页register.3.4.1Dataregister(CRC_DR)Addressoffset:0x00Resetvalue:0xFFFFFFFF4Powercontrol(PWR)Low-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween16and32Kbytes.Medium-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween64and128Kbytes.High-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween256and512Kbytes.XL-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween768Kbytesand1Mbyte.ConnectivitylinedevicesareSTM32F105xxandSTM32F107xxmicrocontrollers.ThissectionappliestothewholeSTM32F10xxxfamily,unlessotherwisespecified.4.1PowersuppliesThedevicerequiresa2.0-to-3.6Voperatingvoltagesupply(VDD).Anembeddedregulatorisusedtosupplytheinternal1.8Vdigitalpower.Thereal-timeclock(RTC)andbackupregisterscanbepoweredfromtheVBATvoltagewhenthemainVDDsupplyispoweredoff.4.1.1IndependentA/DconvertersupplyandreferencevoltageToimproveconversionaccuracy,theADChasanindependentpowersupplywhichcanbeseparatelyfilteredandshieldedfromnoiseonthePCB.TheADCvoltagesupplyinputisavailableonaseparateVDDApin.AnisolatedsupplygroundconnectionisprovidedonpinVSSA.第7页Whenavailable(accordingtopackage),VREF-mustbetiedtoVSSA.On100-pinand144-pinpackagesToensureabetteraccuracyonlowvoltageinputs,theusercanconnectaseparateexternalreferencevoltageADCinputonVREF+andVREF-.ThevoltageonVREF+canrangefrom2.4VtoVDDA.On64-pinpackagesandpackageswithlesspinsTheVREF+andVREF-pinsarenotavailable,theyareinternallyconnectedtotheADCvoltagesupply(VDDA)andground(VSSA).4.1.2BatterybackupdomainToretainthecontentoftheBackupregistersandsupplytheRTCfunctionwhenVDDisturnedoff,VBATpincanbeconnectedtoanoptionalstandbyvoltagesuppliedbyabatteryorbyanothersource.TheVBATpinpowerstheRTCunit,theLSEoscillatorandthePC13toPC15IOs,allowingtheRTCtooperateevenwhenthemaindigitalsupply(VDD)isturnedoff.TheswitchtotheVBATsupplyiscontrolledbythePowerDownResetembeddedintheResetblock.Warning:DuringtRSTTEMPO(temporizationatVDDstartup)orafteraPDRisdetected,thepowerswitchbetweenVBATandVDDremainsconnectedtoVBAT.Duringthestartupphase,ifVDDisestablishedinlessthantRSTTEMPO(RefertothedatasheetforthevalueoftRSTTEMPO)andVDDVBAT+0.6V,acurrentmaybeinjectedintoVBAT第8页throughaninternaldiodeconnectedbetweenVDDandthepowerswitch(VBAT).Ifthepowersupply/batteryconnectedtotheVBATpincannotsupportthiscurrentinjection,itisstronglyrecommendedtoconnectanexternallow-dropdiodebetweenthispowersupplyandtheVBATpin.Ifnoexternalbatteryisusedintheapplication,itisrecommendedtoconnectVBATexternallytoVDDwitha100nFexternalceramicdecouplingcapacitor(formoredetailsrefertoAN2586).WhenthebackupdomainissuppliedbyVDD(analogswitchconnectedtoVDD),thefollowingfunctionsareavailable:PC14andPC15canbeusedaseitherGPIOorLSEpinsPC13canbeusedasGPIO,TAMPERpin,RTCCalibrationClock,RTCAlarmorsecondoutput4.1.3VoltageregulatorThevoltageregulatorisalwaysenabledafterReset.Itworksinthreedifferentmodesdependingontheapplicationmodes.InRunmode,theregulatorsuppliesfullpowertothe1.8Vdomain(core,memoriesanddigitalperipherals).InStopmodetheregulatorsupplieslow-powertothe1.8Vdomain,preservingcontentsofregistersandSRAMInStandbyMode,theregulatorispoweredoff.ThecontentsoftheregistersandSRAMarelostexceptfortheStandbycircuitryandtheBackupDomain.第9页4.2Powersupplysupervisor4.2.1Poweronreset(POR)/powerdownreset(PDR)ThedevicehasanintegratedPOR/PDRcircuitrythatallowsproperoperationstartingfrom/downto2V.ThedeviceremainsinResetmodewhenVDD/VDDAisbelowaspecifiedthreshold,VPOR/PDR,withouttheneedforanexternalresetcircuit.Formoredetailsconcerningthepoweron/powerdownresetthreshold,refertotheelectricalcharacteristicsofthedatasheet.4.3Low-powermodesBydefault,themicrocontrollerisinRunmodeafterasystemorapowerReset.SeverallowpowermodesareavailabletosavepowerwhentheCPUdoesnotneedtobekeptrunning,forexamplewhenwaitingforanexternalevent.Itisuptotheusertoselectthemodethatgivesthebestcompromisebetweenlow-powerconsumption,shortstartuptimeandavailablewakeupsources.TheSTM32F10xxxdevicesfeaturethreelow-powermodes:Sleepmode(CPUclockoff,allperipheralsincludingCortex-M3coreperipheralslikeNVIC,SysTick,etc.arekeptrunning)Stopmode(allclocksarestopped)Standbymode(1.8Vdomainpowered-off)Inaddition,thepowerconsumptioninRunmodecanbereducebyoneofthefollowingmeans:SlowingdownthesystemclocksGatingtheclockstotheAPBandAHBperipheralswhentheyareunused.5Backupregisters(BKP)Low-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xx第10页microcontrollerswheretheFlashmemorydensityrangesbetween16and32Kbytes.Medium-densitydevicesareSTM32F101xx,STM32F102xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween64and128Kbytes.High-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween256and512Kbytes.XL-densitydevicesareSTM32F101xxandSTM32F103xxmicrocontrollerswheretheFlashmemorydensityrangesbetween768Kbytesand1Mbyte.ConnectivitylinedevicesareSTM32F105xxandSTM32F107xxmicrocontrollers.ThissectionappliestothewholeSTM32F10xxxfamily,unlessotherwisespecified.5.1BKPintroductionThebackupregistersarefortytwo16-bitregistersforstoring84bytesofuserapplicationdata.TheyareimplementedinthebackupdomainthatremainspoweredonbyVBATwhentheVDDpowerisswitchedoff.TheyarenotresetwhenthedevicewakesupfromStandbymodeorbyasystemresetorpowerreset.Inaddition,theBKPcontrolregistersareusedtomanagetheTamperdetectionfeatureandRTCcalibration.Afterreset,accesstotheBackupregistersandRTCisdisabledandtheBackupdomain(BKP)isprotectedagainstpossibleparasiticwriteaccess.ToenableaccesstotheBackupregistersandtheRTC,proceedasfollows:enablethepowerandbackupinterfaceclocksbysettingthePWRENandBKPENbitsintheRCC_APB1ENRregister第11页settheDBPbitthePowerControlRegister(PWR_CR)toenableaccesstotheBackupregistersandRTC.5.2BKPmainfeatures20-bytedataregisters(inmedium-densityandlow-densitydevices)or84-bytedataregisters(inhigh-density,XL-densityandconnectivitylinedevices)Status/controlregisterformanagingtamperdetectionwithinterruptcapabilityCalibrationregisterforstoringtheRTCcalibrationvaluePossibilitytooutputtheRTCCalibrationClock,RTCAlarmpulseorSecondpulseonTAMPERpinPC13(whenthispinisnotusedfortamperdetection)5.3BKPfunctionaldescription5.3.1TamperdetectionTheTAMPERpingeneratesaTamperdetectioneventwhenthepinchangesfrom0to1orfrom1to0dependingontheTPALbitintheBackupcontrolregister(BKP_CR).Atamperdetectioneventresetsalldatabackupregisters.HowevertoavoidlosingTamperevents,thesignalusedforedgedetectionislogicallyANDedwiththeTamperenableinordertodetectaTampereventincaseitoccursbeforetheTAMPERpinisenabled.WhenTPAL=0:IftheTAMPERpinisalreadyhighbeforeitisenabled(bysettingTPEbit),anextraTampereventisdetectedassoonastheTAMPERpinisenabled(whiletherewasnorisingedgeontheTAMPERpinafterTPEwasset)WhenTPAL=1:IftheTAMPERpinisalreadylowbeforeitisenabled(bysettingtheTPEbit),anextraTampereventisdetectedassoonastheTAMPERpinis第12页enabled(whiletherewasnofallingedgeontheTAMPERpinafterTPEwasset)BysettingtheTPIEbitintheBKP_CSRregister,aninterruptisgeneratedwhenaTamperdetectioneventoccurs.AfteraTampereventhasbeendetectedandcleared,theTAMPERpinshouldbedisabledandthenre-enabledwithTPEbeforewritingtothebackupdataregisters(BKP_DRx)again.Thispreventssoftwarefromwritingtothebackupdataregisters(BKP_DRx),whiletheTAMPERpinvaluestillindicatesaTamperdetection.ThisisequivalenttoaleveldetectionontheTAMPERpin.Note:TamperdetectionisstillactivewhenVDDpowerisswitchedoff.Toavoidunwantedresettingofthedatabackupregisters,theTAMPERpinshouldbeexternallytiedtothecorrectlevel.5.3.2RTCcalibrationFormeasurementpurposes,theRTCclockwithafrequencydividedby64canbeoutputontheTAMPERpin.ThisisenabledbysettingtheCCObitintheRTCclockcalibrationregister(BKP_RTCCR).Theclockcanbesloweddownbyupto121ppmbyconfiguringCAL6:0bits.FormoredetailsaboutRTCcalibrationandhowtouseittoimprovetimekeepingaccuracy,pleaserefertoAN2604STM32F101xxandSTM32F103xxRTCcalibration”.5.4BKPregistersRefertoSection1.1onpage40foralistofabbreviationsusedinregisterdescriptions.Theperipheralregisterscanbeaccessedbyhalf-words(16-bit)orwords第13页(32-bit).第14页中文翻译稿STM32F103说明1文档约定缩写寄存器1.1清单以下缩写用于寄存器描述：1.2词汇表低密度devicesareSTM32F101xx基本，STM32F102xx和STM32F103xx的微控制器，其中16和32字节的闪存存储器容量范围。中等密度devicesareSTM32F101xx基本，STM32F102xx和STM32F103xx的微控制器，其中64和128字节的闪存存储器容量范围。高密度devicesareSTM32F101xx和STM32F103xx微控制器256和512字节之间的闪存存储器容量范围。XL密度devicesareSTM32F101xx和STM32F103xx微控制器的768KB和1兆字节的闪存存储器容量范围。连接线devicesareSTM32F105xx和STM32F107xx微控制器。字：32位长的数据。半字：16位长的数据。字节：8位长度的数据。1.3外围设备的可用性对于所有的STM32F10xxx销售各类外设的可用性和数量，请参阅低，中，高和XL密度STM32F101xx和STM32F103xx的数据表，以在低收入和中等密度STM32F102xx数据表和到互联型产品，STM32F105xx/STM32F107xx。2存储器和总线架构2.1系统架构在低，中，高和XL密度器件中，主系统包括：四大师：-的Cortex-M3内核的DCode总线（D-总线）和系统总线（S-总线）第15页-GP-DMA12（通用DMA）四个从站：-内部SRAM-内置闪存-FSMC-AHB到APBx（APB1或APB2），它连接所有的APB外设2.2存储器结构程序存储器，数据存储器，寄存器和I/O端口都相同的线性范围内组织4GB的地址空间。该字节编码在内存在小端格式。在一个字的最低编号字节被认为是这个词的最显著字节，编号最高的字节最显著。对于外设寄存器的详细测绘，请参考相关章节。可寻址内存空间分为8个主要模块，每个模块的512MB。所有未分配到片内存储器和外设的内存区域被认为是“保留”）。请参考相应产品的存储器映射图数据表。注：当从SRAM启动，在应用程序初始化代码，你必须重新定位在通过NVIC异常表SRAM和偏移向量表中注册。对于XL密度器件，从主闪存开机时，你有一个选项从任何两个存储体的引导。默认情况下，从Flash存储器组1的引导被选中。您可以选择从Flash存储器组2通过清除用户BFB2位启动选项字节。当该位被清零，启动引脚在从主Flash启动内存配置，从系统内存，并引导装载程序启动设备跳转到执行在Flash存储器组2编程用户应用程序。有关进一步详情，请参考应用笔记AN2606。注：当从银行2开机，在应用程序初始化代码，你必须重新定位矢量表的池Bank2的基地址。（0x08080000）通过NVIC异常表和偏移寄存器。嵌入式引导加载程序嵌入式引导加载程序位于系统内存，在由ST编程生产。它是用来与现有的串行之一重新编程闪存接口：第16页在低，中和高密度器件的bootoader是通过激活USART1接口。在XL密度设备的引导加载程序是通过以下界面激活：USART1USART2或（重映射）。在连接线的设备的引导装载程序可通过一个被激活以下接口：USART1，USART2（重映射），CAN2（重映射）或USBOTG财政司司长在设备模式（DFU：设备固件升级）。该USART外设使用内部8MHz振荡器（HSI）。在CAN和USBOTGFS，但是，只能发挥作用，如果一个外部的8MHz，14.7456MHz或25MHz时钟（HSE）存在。注：欲了解更多详情，请参考应用笔记AN2606。3CRC计算单元低密度devicesareSTM32F101xx基本，STM32F102xx和STM32F103xx的微控制器，其中16和32字节的闪存存储器容量范围。中密度devicesareSTM32F101xx基本，STM32F102xx和STM32F103xx的微控制器，其中64和128字节的闪存存储器容量范围。高密度devicesareSTM32F101xx和STM32F103xx微控制器的256和512字节之间闪存存储器容量范围。XL密度devicesareSTM32F101xx和STM32F103xx微控制器的768KB和1兆字节的闪存存储器容量范围。连接线devicesareSTM32F105xx和STM32F107xx微控制器。本部分适用于整个STM32F10xxx微控制器系列，除非另有规定。3.1CRC的介绍的CRC（循环冗余校验）计算单元，用于从32位得到的CRC码数据字和一个固定的生成多项式。在其他应用中，基于CRC的技术被用于验证数据传输或存储的完整性。在EN/IEC60335-1标准的范围，他们提供的一种手段验证闪存完整性。在CRC计算单元可以计算的签名在运行时软件，以与在链接生成并存储在给定的存储器位置的参考签名进行比较。3.2CRC的主要特点采用CRC-32（以太网）多项式：0x4C11DB7-X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1第17页单输入/输出32位数据寄存器在4AHB时钟周期（HCLK）CRC计算完成通用8位寄存器（可用于临时存储）3.3CRC校验功能描述在CRC计算单元主要由一个单一的32位数据寄存器，其中：被写入时，作为一个输入寄存器，进入在CRC计算器的新数据（该寄存器）保持之前的CRC计算（读寄存器时）的结果每次写操作到数据寄存器创建先前的CRC值的组合和新的（CRC计算的是整个32位数据字完成，并且每字节不字节）。写操作被停止，直到CRC计算的结尾，因此允许背对背写入访问或连续的写和读访问。在CRC计算器可以复位到FFFFFFFFH的同在CRC_CR的RESET控制位登记。此操作不影响CRC_IDR寄存器的内容。3.4CRC寄存器CRC计算单元包含两个数据寄存器和控制寄存器。3.4.1数据寄存器（CRC_DR）地址偏移：为0x00复位值：0xFFFF的FFFF4电源控制（PWR）低密度devicesareSTM32F101xx基本，STM32F102xx和STM32F103xx的微控制器，其中16和32字节的闪存存储器容量范围。中密度devicesareSTM32F101xx基本，STM32F102xx和STM32F103xx的微控制器，其中64和128字节的闪存存储器容量范围。高密度devicesareSTM32F101xx和STM32F103xx微控制器的256和512字节之间闪存存储器容量范围。XL密度devicesareSTM32F101xx和STM32F103xx微控制器的768KB和1兆字节的闪存存储器容量范围。连接线devicesareSTM32F105xx和STM32F107xx微控制器。本部分适用于整个STM32F10xxx微控制器系列，除非另有规定。4.1电源该设备需要一个2.0到3.6V工作电源电压（VDD）。一个嵌入式稳压器第18页是用来提供内部1.8V数字电源。实时时钟（RTC）和备份寄存器可以从VBATvoltage供电时，主要VDDsupply断电。4.1.1独立的A/D转换器的电源和参考电压以提高转换精度，该ADC具有可以是一个独立的电源分别过滤，并从PCB上的噪声屏蔽。ADC的电源输入，可在一个单独的VDDApin。提供引脚VSSA隔离电源的接地连接。当可用（根据包装），VREF-必须连接到VSSA。在100引脚和144引脚封装以确保低电压输入一个更好的精度，用户可以单独连接一个外部在V参考电压ADC输入REF+和VREF-。对V的电压REF+范围可以从2.4V到VDDA。64引脚封装，封装，引脚少VREF+和VREF-引脚不可用，它们在内部连接到ADC电源电压（VDDA）和地（VSSA）。4.1.2电池备份域要保留的备份寄存器的内容，并提供RTC功能当VDD关闭，VBAT引脚可以连接到由电池或提供一个可选的备用电压另一个来源。该VBATpin权力RTC单位，LSE振荡器和PC13PC15到的IO，允许在RTC到即使主数字电源（VDD）被关断操作。切换到VBATsupply由掉电复位嵌入复位模块控制。警告：在tRSTTEMPO（因循于VDDstartup）或PDR后被检测到，V之间的电源开关BAT和VDDremains连接到VBAT。在启动阶段，如果VDDis成立小于tRSTTEMPO（请参阅数据表tRSTTEMPO的值）第19页和VDDVBAT+0.6V，电流可以被注入到VBAT通过连接VDDand之间的内部二极管电源开关（VBAT）。如果电源/电池连接到VBATpin不能支持这个电流注入，强烈推荐连接这个电源之间的外部低压降二极管供应和VBATpin。如果没有外部电池中使用的应用程序，它是推荐连接V英美烟草公司内外兼修VDDwith一个100nF的外部陶瓷去耦电容（详细内容见到AN2586）。当备份域是由VDD（连接到VDD模拟开关），所提供的提供以下功能：PC14和PC15可被用作GPIO或LSE标签PC13可以作为GPIO，防拆针，RTC校准时钟，RTC闹钟或第二个输出4.1.3电压调节器电压调节器复位后始终处于启用状态。它工作在三种不同的模式根据不同的应用模式。在运行模式下，稳压电源全功率到1.8V（内核，存储器和数字外设）。在停止模式下，稳压器提供低功耗的1.8V电源，保护寄存器和SRAM的内容在待机模式下，稳压器的电源关闭。寄存器和SRAM的内