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TheDescriptionofAT89S511GeneralDescriptionTheAT89S51isalowpower,highperformanceCMOS8bitmicrocontrollerwith4KbytesofInSystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmelshighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80C51instructionsetandpinout.TheonchipFlashallowstheprogrammemorytobereprogrammedinsystemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8bitCPUwithInSystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.TheAT89S51providesthefollowingstandardfeatures4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16bittimer/counters,afivevectortwolevelinterruptarchitecture,afullduplexserialport,onchiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePowerdownmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.2PortsPort0isan8bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0canalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1isan8bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpullups.Port1alsoreceivestheloworderaddressbytesduringFlashprogrammingandverification.Port2isan8bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpullups.Port2emitsthehighorderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16bitaddressesMOVXDPTR.Inthisapplication,Port2usesstronginternalpullupswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8bitaddressesMOVXRI,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehighorderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3isan8bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseofthepullups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.3SpecialFunctionRegistersAmapoftheonchipmemoryareacalledtheSpecialFunctionRegisterSFRspaceisshowninTable51.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.InterruptRegistersTheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.DualDataPointerRegistersTofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16bitDataPointerRegistersareprovidedDP0atSFRaddresslocations82H83HandDP1at84H85H.BitDPS0inSFRAUXR1selectsDP0andDPS1selectsDP1.TheusershouldALWAYSinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.PowerOffFlagThePowerOffFlagPOFislocatedatbit4PCON.4inthePCONSFR.POFissetto1duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.4MemoryOrganizationMCS51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.4.1ProgramMemoryIftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S51,ifEAisconnectedtoVCC,programfetchestoaddresses0000HthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory.4.2DataMemoryTheAT89S51implements128bytesofonchipRAM.The128bytesareaccessibleviadirectandindirectaddressingmodes.Stackoperationsareexamplesofindirectaddressing,sothe128bytesofdataRAMareavailableasstackspace.7.WatchdogTimerOnetimeEnabledwithResetoutTheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14bitcounterandtheWatchdogTimerResetWDTRSTSFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregisterSFRlocation0A6H.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreseteitherhardwareresetorWDToverflowreset.WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.5UsingtheWDTToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregisterSFRlocation0A6H.WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The14bitcounteroverflowswhenitreaches163833FFFH,andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery16383machinecycles.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawriteonlyregister.TheWDTcountercannotbereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRSTpin.TheRESETpulsedurationis98xTOSC,whereTOSC1/FOSC.TomakethebestuseoftheWDT,itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset.InPowerdownmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPowerdownmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPowerdownmodebyahardwareresetorviaalevelactivatedexternalinterrupt,whichisenabledpriortoenteringPowerdownmode.WhenPowerdownisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheAT89S51isreset.ExitingPowerdownwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPowerdownmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPowerdown,itisbesttoresettheWDTjustbeforeenteringPowerdownmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLEWDIDLEbit0asthedefaultstate.TopreventtheWDTfromresettingtheAT89S51whileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.Timer0andTimer1intheAT89S51operatethesamewayasTimer0andTimer1intheAT89C51.Forfurtherinformationonthetimersoperation,pleaseclickonthedocumentlinkbelowhttp//www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF6InterruptsTheAT89S51hasatotaloffiveinterruptvectorstwoexternalinterruptsINT0andINT1,twotimerinterruptsTimers0and1,andtheserialportinterrupt.TheseinterruptsareallshowninFigure101.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatTable101showsthatbitpositionsIE.6andIE.5areunimplemented.Usersoftwareshouldnotwrite1stothesebitpositions,sincetheymaybeusedinfutureAT89products.TheTimer0andTimer1flags,TF0andTF1,aresetatS5P2ofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.7OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanonchiposcillator,asshowninFigure111.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdriven,asshowninFigure112.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadividebytwoflipflop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
编号:201311171100565643    大小:51.00KB    格式:DOC    上传时间:2013-11-17
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