交通灯信号控制设计_.doc

eda技术实验报告册班级： 姓名：学号：指导教师：开课时间: 2013 至 2014 学年第 1 学期实验名称交通灯信号控制设计实验时间2013年12月05日姓 名实验成绩一、实验目的1.掌握vhdl语言的基本结构。2.掌握vhdl层次化的设计方法。3.掌握vhdl基本逻辑电路的综合设计应用。二、实验设备计算机软件：quartus iieda实验箱。主芯片：epm7128slc84-15或ep1k100qc208-3。下载电缆，导线等。三、实验内容设计并调试好一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器，具体要求如下：1.主、支干道各设一个绿、黄、红指示灯，两个显示数码管。2.主干道处于常允许通行状态，而支干道有车来时才允许通行。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯。3.当主、支干道均有车时，两者交替允许通行，主干道每次放行45s，支干道每次放行25s，在每次由亮绿灯变成亮红灯的转换过程中，要亮5s的黄灯作为过渡，并进行减计时显示。要求编写交通灯控制器电路逻辑图中的各个模块的vhdl语言程序，并完成交通灯控制器的顶层设计，然后利用开发工具软件对其进行编译和仿真，最后要通过实验开发系统对其进行硬件验证。（一）编写交通灯控制器jtdkz模块的vhdl程序，并对其进行编译和仿真，初步验证设计的正确性。library ieee;use ieee.std_logic_1164.all;entity jtdkz isport(clk, sm, sb: in std_logic;mr, my, mg, br, by, bg: out std_logic);end entity jtdkz;architecture art of jtdkz istype state_type is(a, b, c, d);signal state: state_type;signal cnt:integer range 0 to 45;begin process(clk) isbeginif(clkevent and clk=1)thencase state is when a= if(sb and sm)=1 thenif cnt=44 then cnt=0; state=b;else cnt=cnt+1;state=a; end if; elsif(sb and (not sm)=1 thenstate=b; cnt=0; else state=a; cnt if cnt=4 then cnt=0;state=c; else cnt=cnt+1;state if(sm and sb)=1 then if cnt=24 then cnt=0; state=d; else cnt=cnt+1;state=c; end if; elsif sb=0 then state=d; cnt=0; else state=c; cnt if cnt=4 then cnt=0; state=a; else cnt=cnt+1;statemr=0; my=0; mg=1;br=1; by=0; bgmr=0; my=1; mg=0;br=1; by=0; bgmr=1; my=0; mg=0;br=0; by=0; bgmr=1; my=0; mg=0;br=0; by=1; bg=0;end case; end process rgy;end architecture art;（二）编写45s定时单元cnt45s模块的vhdl程序，并对其进行编译和仿真，初步验证设计的正确性。-45s定时模块源程序cnt45s.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_45s is port(sb,sm, clk, en45: in std_logic; dout45m, dout45b: out std_logic_vector(7 downto 0); end entity time_45s ; architecture art of time_45s is signal cnt6b: std_logic_vector(5 downto 0); begin process(sb, sm, clk, en45) is begin if(clkevent and clk= 1)then if sb=1 and sm=1 then if en45=1then cnt6b=cnt6b+1;else cnt6b=000000; end if; else cnt6bdout45m=01000101; dout45bdout45m=01000100; dout45bdout45m=01000011; dout45bdout45m=01000010; dout45bdout45m=01000001; dout45bdout45m=01000000; dout45bdout45m=00111001; dout45bdout45m=00111000; dout45bdout45m=00110111; dout45bdout45m=00110110; dout45bdout45m=00110101; dout45bdout45m=00110100; dout45bdout45m=00110011; dout45bdout45m=00110010; dout45bdout45m=00110001; dout45bdout45m=00110000; dout45bdout45m=00101001; dout45bdout45m=00101000; dout45bdout45m=00100111; dout45bdout45m=00100110; dout45bdout45m=00100101; dout45bdout45m=00100100; dout45bdout45m=00100011; dout45bdout45m=00100010; dout45bdout45m=00100001; dout45bdout45m=00100000; dout45bdout45m=00011001; dout45bdout45m=00011000; dout45bdout45m=00010111; dout45bdout45m=00010110; dout45bdout45m=00010101; dout45bdout45m=00010100; dout45bdout45m=00010011; dout45bdout45m=00010010; dout45bdout45m=00010001; dout45bdout45m=00010000; dout45bdout45m=00001001; dout45bdout45m=00001000; dout45bdout45m=00000111; dout45bdout45m=00000110; dout45bdout45m=00000101; dout45bdout45m=00000100; dout45bdout45m=00000011; dout45bdout45m=00000010; dout45bdout45m=00000001; dout45bdout45m=00000000; dout45b=00000000; -bcd数00, 00 end case; end process; end architecture art;（三）编写25s定时单元cnt25s模块的vhdl程序，并对其进行编译和仿真，初步验证设计的正确性。-25s定时模块源程序cnt25s.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_25s is port(sb, sm, clk, en25: in std_logic; dout25m, dout25b: out std_logic_vector(7 downto 0); end entity time_25s; architecture art of time_25s is signal cnt_5bit: std_logic_vector(4 downto 0); begin process(sb, sm, clk, en25) is begin if sb=0 or sm=0 then cnt_5bit=00000; elsif(clkevent and clk= 1)then if en25=1 then cnt_5bit=cnt_5bit+1; elsif en25=0then cnt_5bitdout25b=00100101; dout25mdout25b=00100100; dout25mdout25b=00100011; dout25mdout25b=00100010; dout25mdout25b=00100001; dout25mdout25b=00100000; dout25mdout25b=00011001; dout25mdout25b=00011000; dout25mdout25b=00010111; dout25mdout25b=00010110; dout25mdout25b=00010101; dout25mdout25b=00010100; dout25mdout25b=00010011; dout25mdout25b=00010010; dout25mdout25b=00010001; dout25mdout25b=00010000; dout25mdout25b=00001001; dout25mdout25b=00001000; dout25mdout25b=00000111; dout25mdout25b=00000110; dout25mdout25b=00000101; dout25mdout25b=00000100; dout25mdout25b=00000011; dout25mdout25b=00000010; dout25mdout25b=00000001; dout25mdout25b=00000000; dout25m=00000000; -bcd数00, 00 end case; end process; end architecture art;（四）编写5s定时单元cnt05s模块的vhdl程序，并对其进行编译和仿真，初步验证设计的正确性。-5s定时模块源程序cnt05s.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_5s is port(clk, en05m, en05b: in std_logic; dout5: out std_logic_vector(7 downto 0); end entity time_5s; architecture art of time_5s is signal cnt_3bit: std_logic_vector(2 downto 0); begin process(clk, en05m, en05b) is begin if(clkevent and clk= 1)then if en05m=1 or en05b=1 then cnt_3bit=cnt_3bit+1; else cnt_3bitdout5dout5dout5dout5dout5dout5=00000000; -bcd数00 end case; end process; end architecture art;（五）编写显示控制单元xskz模块的vhdl程序，并对其进行编译和仿真，初步验证设计的正确性。-显示控制模块源程序xskz.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity xskz is port(en45, en25, en05m, en05b:in std_logic; ain45m, ain45b: in std_logic_vector(7 downto 0); ain25m, ain25b, ain05: in std_logic_vector(7 downto 0); dec_m, dec_b: out std_logic_vector(7 downto 0); end entity xskz; architecture art of xskz is begin process(en45,en25,en05m, en05b,ain45m,ain45b,ain05,ain25m,ain25b) is begin if en45=1 then dec_m=ain45m(7 downto 0); dec_b=ain45b(7 downto 0); elsif en05m=1 then dec_m=ain05(7 downto 0); dec_b=ain05(7 downto 0); elsif en25=1 then dec_m=ain25m(7 downto 0); dec_b=ain25b(7 downto 0); -elsif en05b=1 then else dec_m=ain05(7 downto 0); dec_b=ain05(7 downto 0); end if; end process; end architecture art; （六）数码管动态扫描显示电路设计library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity disp_scan is port(clk_scan: in std_logic; dec_m: in std_logic_vector(7 downto 0); dec_b: in std_logic_vector(7 downto 0); ledw: out std_logic_vector(2 downto 0); seg7: out std_logic_vector(7 downto 0); end entity disp_scan; architecture art of disp_scan issignal temp: std_logic_vector(3 downto 0);signal cnt:std_logic_vector(2 downto 0); begin process(clk_scan) is begin if clk_scanevent and clk_scan=1 then if cnt=111 then cnt=000; else cnt=cnt+1; end if; end if; end process; ledw temp temp temp temp temp seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7=00000000; end case; end process; end architecture art;（七）利用前面所设计的模块，完成交通灯信号控制器的顶层设计，并对其进行编译和仿真，初步验证设计的正确性。library ieee;use ieee.std_logic_1164.all;entity traffic isport(sb,sm, clk, clk_scan: in std_logic;mr1,my1,mg1,br1,by1,bg1:buffer std_logic;-mr2,my2,mg2,br2,by2,bg2:out std_logic;ledw:out std_logic_vector(2 downto 0);seg7: out std_logic_vector(7 downto 0);end entity traffic ;architecture art of traffic iscomponent jtdkz isport(clk, sm, sb: in std_logic;mr, my, mg, br, by, bg: out std_logic);end component jtdkz; component time_45s is port(sb,sm, clk, en45: in std_logic; dout45m, dout45b: out std_logic_vector(7 downto 0); end component time_45s ; component time_25s is port(sb, sm, clk, en25: in std_logic; dout25m, dout25b: out std_logic_vector(7 downto 0); end component time_25s;component time_5s is port(clk, en05m, en05b: in std_logic; dout5: out std_logic_vector(7 downto 0); end component time_5s; component xskz is port(en45, en25, en05m, en05b:in std_logic; ain45m, ain45b: in std_logic_vector(7 downto 0); ain25m, ain25b, ain05: in std_logic_vector(7 downto 0); dec_m, dec_b: out std_logic_vector(7 downto 0); end component xskz; component disp_scan is port(clk_scan: in std_logic; dec_m: in std_logic_vector(7 downto 0); dec_b: in std_logic_vector(7 downto 0); ledw: out std_logic_vector(2 downto 0); seg7: out std_logic_vector(7 downto 0); end component disp_scan; signal data_45m: std_logic_vector(7 downto 0);signal data_45b: std_logic_vector(7 downto 0);signal data_25m :std_logic_vector(7 downto 0);signal data_25b :std_logic_vector(7 downto 0);signal data_05 :std_logic_vector(7 downto 0);signal dec_m :std_logic_vector(7 downto 0);signal dec_b :std_logic_vector(7 downto 0);begin u0:jtdkz port map(clk,sm,sb,mr1,my1,mg1,br1,by1,bg1); u1:time_45s port map(sb,sm,clk,mg1,data_45m,data_45b); u2:time_25s port map(sb,sm,clk,bg1,data_25m,data_25b); u3:time_5s port map(clk,my1,by1,data_05); u4:xskz port map(mg1,bg1,my1,by1,data_45m,data_45b,data_25m,data_25b,data_05,dec_m,dec_b ); u5:disp_scan port map(clk_scan,dec_m,dec_b,ledw,seg7);end architecture art;（八）逻辑综合结果使用quartus 进行逻辑综合，给出电路的 rtl视图及逻辑综合后的资源使用情况。（九）管脚锁定及硬件验证情况按如下要求进行引脚锁定：set_location_assignment pin_78 -to clkset_location_assignment pin_79 -to clk_scanset_location_assignment pin_53 -t