时钟精度要求确定为UART的通讯外文翻译.docx

科技文章摘译 英文原文 determining clock accuracy requirements for uart communicationsabstract: this application note discusses the timing requirements for the commonly used serial asynchronous communications protocol implemented in uarts, and shows how to determine the tolerance for the uart clock source at both ends of an asynchronous link.backgroundthe rs-232 specification dates back to 1962, when it was first released by the eia (electronic industries association). the specification has changed over time, incorporating higher data rates and closing the compatibility gaps between tia (telecommunication industry association) and international (itu, iso) standards. the current version of the rs-232 specification is eia/tia-232-f, dated october 1997. the protocol benefited from the availability of msi ics from the late 1970s which had the complexity to handle the standard at reasonable cost. these ics are generically called uarts (universal asynchronous receive transmit). many lsi ics (including microcontrollers) now include the functionality.as is often the case, the availability of uarts drove the industry to use the rs-232 serial protocol in non-rs-232 ways. common examples are rs-485 transmissions, opto-isolated transmissions, and transmissions using a single-ended physical layer (i.e. 0 - 3.3v instead of 5v or 10v). this note covers the general timing aspects of the serial interface, not application nuances of handshaking or the physical layer, and so is applicable to all generalized uart applications.uart timinga typical uart frame is shown in figure 1. it comprises a start bit, 8 data bits, and a stop bit. other variants are also possible in rs-232 applications - the data packet could be 5, 6, or 7 bits long, there could be 2 stop bits, and a parity bit could be inserted between the data packet and the stop bit for rudimentary error detection. figure 1 shows the signaling as seen at a uarts txd (transmit data) or rxd (receive data) pins. rs-232 bus drivers invert as well as level shift, so a logic 1 is a negative voltage on the bus, and a logic 0 is a positive voltage. figure 1. a typical uart data frame.when two uarts communicate, it is a given that both transmitter and receiver know the signaling speed. the receiver doesnt know when a packet will be sent, with respect to the receiver clock, hence the protocol is termed asynchronous. the receiver circuitry is correspondingly more complex than that of the transmitter. while the transmitter simply has to shuffle out a frame of data at a defined bit rate, the receiver has to recognize the start of the frame to synchronize itself, and therefore determine the best data sampling point for the bitstream.figure 2 shows a common method used by uart receivers to synchronize to a received frame. the receive uart uses a clock which is 16 times the data rate. a new frame is recognized by the falling edge at the beginning of the active-low start bit, when the signal changes from the active-high stop bit or bus idle condition. the receive uart resets its counters on this falling edge, and expects mid start bit to occur after 8 clock cycles, and the mid point of each subsequent bit to appear every 16 clock cycles thereafter. the start bit is typically sampled at the mid bit time to check that the level is still low, to ensure that the detected falling edge was a start bit not a noise spike. another common improvement is to sample each bit not simply once at the mid bit position (clock count 8 out of 16), but three times (clock counts 7, 8, and 9 out of 16).figure 2. uart receive frame synchronization and data sampling points.timing accuracyso the question is: how accurate does the receive uart clock have to be to be sure of receiving data correctly? (actually, a better question is to ask how far different the transmit and receive uart clocks can be, since the absolute clock rate is unimportant for the purposes of accurate reception. more on this later.) to answer this, the first point to understand is that because the uart receiver synchronizes itself to the start of each and every frame, we only care about accurate data sampling during one frame. there isnt any buildup of error beyond a frames stop bit, which simplifies analysis because we only have to consider one frame as the worst case. when do we get a timing error due to transmit-receive clock mismatch? well, we are attempting to sample each bit at the mid point (figure 2). if we sample a bit a bit period too early or too late, we will sample at the bit transition and have problems (figure 3).figure 3. uart receive sampling range.in reality, we cant (reliably) sample close to the bit transition point. the dominant reason for this is the finite (and typically slow) transmission rise and fall times, made even slower if overly capacitive cabling is used. a long bus incurs high attenuation, reducing noise margin, making it more important to sample when the bit level has settled. it is difficult to assess a worst case acceptable sampling range across a bits period in a quantitive manner. eia/tia-232-f does specify a 4% of bit period maximum slew time for a transmission, but this is difficult to achieve for long runs at 192k/bits-1. but let us define two data path scenarios for the purpose of this note. consider a nasty scenario which can only be sampled reliably within the middle 50% of the bit time (figure 4). this could equate to a long, capacitive rs-232 run. the normal scenario can be sampled within the middle 75% of the bit time (figure 5), equating to a relatively benign bus (such as a metre or two run with buffered cmos logic levels or an rs-485 differential pair) within an equipment chassis.for figures 4 and 5 we can determine that the error budget is 25% and 37.5% from the optimal bit-centre sampling point for the nasty and normal scenarios respectively. this error is equivalent to 4 or 6 periods of the x16 uart receive clock. another error to include in this budget is the synchronization error when the falling edge of the start bit is detected. the uart will most likely be designed to start on the next rising edge of its 16x clock after start bit detection. since the 16x clock and the received data stream are asynchronous, the falling edge of the start bit could occur just after a 16x clock rising edge, or just before one but not with enough setup time to use it. this means that the uart has a 1 bit error built in at the synchronization point. so our error budget reduces from 4 or 6 clock periods to 3 or 5 periods.we will presume that short-term clock errors (essentially, jitter) are very small, and therefore we are only considering mid-term and long-term errors. these errors boil down to mismatch in the transmit uart and receive uart timing that is consistent during a frame. since the timing is synchronized at the falling edge of the start bit, the worst case timing error will be at the last data sampling point, which is the stop bit. the optimum sampling point for the stop bit is are its bit-centre, which is (16 x 9.5) = 152 uart receive clocks after the original falling edge of the start bit.now we can calculate our allowable error as a percentage. for the normal scenario, the clock mismatch error can be 5/152 = 3.3%, and for the nasty scenario it can be 3/152 = 2%. as hinted earlier, although the problem will materialize at the receive end of the link, clock mismatch is actually a tolerance issue shared between the transmit and receive uarts. so presuming that both uarts are attempting to communicate at exactly the same bit rate (baud), then the allowable error can be shared, in any proportion, between the two uarts.making use of the allowable error budget is helped in systems where both ends of the link are being designed at the same time, partly because the tolerance of both ends will be known, and partly because tradeoffs and cost saving can be made. in general a standard, low cost, ceramic resonator with 0.5% accuracy and a further 0.5% drift over temperature and life can be used for the clock source at both ends of the link. this meets the 2% nasty scenario discussed earlier. if the system uses a master controller (typically a microcontroller or a pc) which uses a standard 100ppm crystal oscillator for the uart clock source, then the link error just about halves. be careful with microcontrollers that synthesize baud frequencies for their internal uarts. depending on the choice of microcontroller clock, the baud rates may not be exact. if the error can be determined, it can be easily included in the link error budget.1. it may appear odd that the stop bit is sampled, but it is. if the stop bit is detected as a low level instead of the expected high level, uarts typically report a frame error.英文译文 时钟精度要求确定为uart的通讯文摘:本应用笔记讨论时间要求,常用的串行通信协议执行uarts同步,并展示了如何确定宽容uart源两端的时钟的同步连接。背景,这个rs-232规格可追溯至1962年,当它首先被释放的环境影响评价(电子工业协会)。规格已经改变了,随着时间的推移,高数据率将关闭相容性之间的差距(电信行业协会的症状及国际(itu)标准,国际标准化组织(iso)。当前版本的rs-232规格环评/ tia-232-f约会,1997年10月。这个协议中获益的芯片的中型从20世纪70年代的复杂性来处理这个标准,能以合理的价格。这些电路是一般称为uarts(通用异步接收传输)。许多大规模集成电路芯片(包括微控制器)现在包括功能。通常情况下,uarts把工业用rs-232串行协议在non-rs-232方式。常见的例子是rs-485传输,opto-isolated变速箱、变速器结束单人赛物理层(如下。0 - 3.3v代替5伏或10伏特)。这张封面一般时间方面的串行接口,不申请的细微差别,或实体层,握手,适用于所有的程序。uart广义uart时间一个典型的uart架载于本许可证图1。它包括一个起始位元,8位元的资料,并停止位。也可能在其他变量的数据包rs-232应用-可5、6、7位长的话,将会有2个停止位、一同等值位可以插入的数据间的包,停止位为基本错误检测。图1显示如图一个uart信号传输数据的txd(或rxd(接收数据)。公共汽车司机rs-232反演以及水平移动,所以一个逻辑1负电压在公共汽车上,一个逻辑0是一个积极的电压。图1。一个典型的uart数据帧。当两个uarts沟通,它是一种已知的事实都发射机和接收机信号速度。知道接收者不知道当一个包,就会发送给接受者的钟,于是这个协议是异步的。相应的接收机电路是更复杂的发射机。而从发射机只需要简单地洗牌一帧的数据在一个定义编码传输率、接收器已认识到开始的帧同步,确定最佳的数据采集的最高。图2所示的常用方法采用同步uart接收机收到的框架。用一个时钟的接收uart的数据速率16倍。一个新的框架是公认的下降沿active-low之初,当信号的起始位高电平次数的变化的停止位或巴士闲置状态。接收uart重置其柜台边,并且希望这个下降中发生在8点开始,中期时钟周期后续的每一个点对点出现每16时钟周期。一开始是典型的采样点的时间来检查中期的水平仍然很低,确保检测是起始位下降沿不是噪音。另一个常见的进步是抽样检查每一点不只是一次中期位(时钟计数8个),但三次(时钟计数7、8、9 / 16)。图2。收到帧同步和数据的uart采样点。时间精度所以问题是:如何精确的接收uart时钟都必须确信接收数据的正确吗?实际上,一个更好的问题(就是问迥然不同的传输和接收uart钟可以,因为绝对的时钟频率是无足轻重的精确的接待。在这之后。)要回答这个问题,首先是要了解:因为uart接收器本身的同步、每帧,我们只关心精确的数据采集在一架。没有任何累积误差超过了框架的停止位、简化分析,因为我们不得不考虑一帧作为最坏的情况。当我们得到一个计时误差transmit-receive时钟匹配吗?好了,我们都试图在中期,每点样点(图2)。如果我们样品经过一点一点时期太早或太迟了,我们将样品,过渡和有问题(图3)。图3。接受抽样范围。uart事实上,我们不能(可靠)样品到发际线。主导的原因是有限的(通常是慢传输的上升和下降,甚至如果过度电容式布线是慢。很长一段时间,减少汽车亦高噪音衰减,使它更重要的边缘点样时的水平已经得到解决。很难评估一个坏的情况下,可接受的取样范围横跨一点点定量方式的时期。tia-232-f做环评/指定一个4