VHDL与数字电路设计PPT课件-第五章 组合逻辑电路的设计.ppt

第五章 组合逻辑 电路的设计,vhdl与数字电路设计,联系电话：52334039 e-mail：,2005年6月11日,2,电路单元分类,本章内容,基本门电路 编码器和译码器 数据选择器和数据分配器 算术逻辑单元（alu）,任一时刻的输出仅仅取决于当时的输入，与电路原来的状态无关，这样的数字电路叫做组合逻辑电路。,1、基本门电路,与、或、非门,library ieee; use ieee.std_logic_1164.all; entity basic_gate is port(a,b: in std_logic; y1,y2,y3: out std_logic); end basic_gate; architecture behave of basic_gate is begin y1 = a and b; y2 = a or b; y3 = not a; end behave;,基本门的行为描述：,architecture rtl of basic_gate is begin process(a,b) -与门 variable ab: std_logic_vector(1 downto 0); begin ab = a ,基本门的数据流描述：,与非门、或非门、异或门、异或非门 y1 = not (a and b); y2 = not (a or b); y3 = (a and (not b) or (not a) and b); y4 = not y3; 三态门,en,din,dout,三态门电路的真值表,三态门的vhdl行为描述如下：,library ieee; use ieee.std_logic_1164.all; entity tristate_gate is port(din,en: in std_logic; dout: out std_logic); end tristate_gate; architecture behave of tristate_gate is begin process(din,en) begin if (en = 1) then dout = din; else dout = z; end if; end process; end behave;,2.1、编码器:,2、编码器和译码器,library ieee; use ieee.std_logic_1164.all; entity encoder is port(a : in std_logic_vector(7 downto 0); y : out std_logic_vector(2 downto 0); end encoder; architecture rtl1 of encoder is begin process(a) begin if a= “00000001” then y= “000”; elsif a= “00000010” then y= “001”; elsif a= “00000100” then y= “010”; elsif a= “00001000” then y= “011”; elsif a= “00010000” then y= “100”; elsif a= “00100000” then y= “101”; elsif a= “01000000” then y= “110”; elsif a =“10000000” then y= “111”; else y= “zzz”; end if; end process; end rtl1;,library ieee; use ieee.std_logic_1164.all; entity encoder is port(a : in std_logic_vector(7 downto 0); y : out std_logic_vector(2 downto 0); end encoder; architecture rtl2 of encoder is begin with a select y= “000“ when “00000001“, “001“ when “00000010“, “010“ when “00000100“, “011“ when “00001000“, “100“ when “00010000“, “101“ when “00100000“, “110“ when “01000000“, “111“ when “10000000“, “zzz“ when others; end rtl2;,2.2、3-8译码器:,library ieee; use ieee.std_logic_1164.all; entity decoder is port(y : in std_logic_vector(2 downto 0); en : in std_logic; a : out std_logic_vector(7 downto 0); end decoder; architecture rtl of decoder is signal sel : std_logic_vector(3 downto 0); begin sel=en ,3、数据选择器和数据分配器,3.1 数据选择器 3.2 数据分配器,1-8 dmux,d,s2,s1,s0,y0,y7,en,library ieee; use ieee.std_logic_1164.all; entity dmux1_8 is port(d,en,s2,s1,s0: in std_logic; y: out std_logic); end dmux1_8; architecture rtl of dmux1_8 is signal comb: std_logic_vector(2 downto 0); begin comb = s2 ,elsif (comb = “001”) then y(1) z); end if; end process; end rtl;,4、算术逻辑单元（alu）,（1）算术电路单元的设计 （2）逻辑电路单元的设计 （3） 21数据选择器的设计,alu运算功能,library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity malu is generic(n : integer:=8); port( s : in std_logic_vector(2 downto 0); -运算功能选择信号 cin : in std_logic; -初始进位 a,b : in std_logic_vector(n-1 downto 0); -两个运算输入信号 f : out std_logic_vector(n-1 downto 0); -运算结果输出信号 cout: out std_logic); -运算进位输出信号 end malu; architecture arith of malu is signal f1 : std_logic_vector(n downto 0); -保存算术运算结果 signal f2 : std_logic_vector(n-1 downto 0); -保存逻辑运算结果 begin,b1: block begin process(s(1 downto 0),a,b,cin) begin case s(1 downto 0) is when “00“= f1f1 f1 f1 f2 f