基于DDS信号技术的信号发生器的设计.doc

基于dds信号技术的信号发生器的设计直接数字式频率合成技术dds是新一代的频率合成技术，采用数字控制信号的相位增加技术，具有频率分辨率高，频率切换快，频率切换时相位连续和相位噪声低以及全数字化易于集成等优点而被广泛采用。一 程序代码（1） adder32blibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder32b isport(ain : in std_logic_vector(31 downto 0);bin : in std_logic_vector(31 downto 0);cout: out std_logic_vector(31 downto 0);end;architecture one of adder32b isbegincout = ain + bin;end;（2）juxing_romlibrary ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity juxing_rom isport(address: in std_logic_vector (11 downto 0);clock: in std_logic ;q: out std_logic_vector (7 downto 0);end juxing_rom;architecture syn of juxing_rom issignal sub_wire0: std_logic_vector (7 downto 0);component altsyncramgeneric (address_aclr_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (11 downto 0);q_a: out std_logic_vector (7 downto 0);end component;beginq none,init_file = ./mif/juxing.mif,intended_device_family = cyclone,lpm_hint = enable_runtime_mod=no,lpm_type = altsyncram,numwords_a = 4096,operation_mode = rom,outdata_aclr_a = none,outdata_reg_a = clock0,widthad_a = 12,width_a = 8,width_byteena_a = 1)port map (clock0 = clock,address_a = address,q_a = sub_wire0);end syn;（3）mux3_1library ieee;use ieee.std_logic_1164.all;entity mux3_1 isport( sin:in std_logic_vector(7 downto 0); sanjiao,juxing:in std_logic_vector(7 downto 0); a,b:in std_logic; cout:out std_logic_vector(7 downto 0);end mux3_1;architecture behavior of mux3_1 issignal addr:std_logic_vector(1 downto 0);begin process(a,b) begin addr(0)=a; addr(1) cout cout cout null; end case; end process;end behavior;（4）sanjiao_romlibrary ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity sanjiao_rom isport(address: in std_logic_vector (11 downto 0);clock: in std_logic ;q: out std_logic_vector (7 downto 0);end sanjiao_rom;architecture syn of sanjiao_rom issignal sub_wire0: std_logic_vector (7 downto 0);component altsyncramgeneric (address_aclr_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (11 downto 0);q_a: out std_logic_vector (7 downto 0);end component;beginq none,init_file = ./mif/sanjiao.mif,intended_device_family = cyclone,lpm_hint = enable_runtime_mod=no,lpm_type = altsyncram,numwords_a = 4096,operation_mode = rom,outdata_aclr_a = none,outdata_reg_a = clock0,widthad_a = 12,width_a = 8,width_byteena_a = 1)port map (clock0 = clock,address_a = address,q_a = sub_wire0);end syn;（5）sinx256_romlibrary ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity sinx256_rom isport(address: in std_logic_vector (7 downto 0);inclock: in std_logic ;q: out std_logic_vector (7 downto 0);end sinx256_rom;architecture syn of sinx256_rom issignal sub_wire0: std_logic_vector (7 downto 0);component altsyncramgeneric (address_aclr_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (7 downto 0);q_a: out std_logic_vector (7 downto 0);end component;beginq none,init_file = ./mif/sinx256_rom.mif,intended_device_family = cyclone,lpm_hint = enable_runtime_mod=no,lpm_type = altsyncram,numwords_a = 256,operation_mode = rom,outdata_aclr_a = none,outdata_reg_a = clock0,widthad_a = 8,width_a = 8,width_byteena_a = 1)port map (clock0 = inclock,address_a = address,q_a = sub_wire0);end syn;（6）reg32blibrary ieee;use ieee.std_logic_1164.all;entity reg32b isport(clk : in std_logic;din : in std_logic_vector(31 downto 0);dout: out std_logic_vector(31 downto 0);end;architecture one of reg32b isbeginprocess(clk,din)beginif clkevent and clk = 1 thendout = din;end if;end process;-dout = passer ;end;（6）sinlibrary ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity sin isport(address: in std_logic_vector (7 downto 0);clock: in std_logic ;q: out std_logic_vector (7 downto 0);end sin;architecture syn of sin issignal sub_wire0: std_logic_vector (7 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (7 downto 0);q_a: out std_logic_vector (7 downto 0);end component;beginq bypass,clock_enable_output_a = bypass,init_file = ./sin.mif,intended_device_family = stra