verilog实现串并与并串转换.docx

Abstract在實務上常常需要將parallel轉成serial，然後再將serial轉成parallel，本文討論如何實現這些功能。Introduction使用環境：NC-Verilog 5.4 + Debussy 5.4 v9 + Quartus II 7.2很多介面都採用serial傳輸，如I2C、LVDS、mini-LVDS等，在寫入時必須將parallel資料轉成serial，讀出時又得將serial轉成parallel，所以是個常用的電路，其原理就是使用shift register來達成，本文將一一討論parallel轉serial，serial轉parallel，也順便討論parallel轉parallel與serial轉serial。並進串出 (Parallel In Serial Out)當load為1且clk rising edge時，parallel data載入至register當中，當load為0且clk rising edge時，register資料依序往前遞移，在最後一個register將資料送出。p2s.v / Verilog1/*2(C) OOMusou 2009 34Filename : p2s.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Synthesizer : Quartus II 7.27Description : parallel in serial out rtl8Release : Oct/24/2009 1.09*/1011module p2s (12 clk,13 rst_n,14 load,15 pi,16 so17);1819input clk;20input rst_n;21input load;22input 3:0 pi;23output so;2425reg 3:0 r;2627always(posedge clk ornegedge rst_n) 28 if (rst_n)29 r =4h0;30 elseif (load)31 r = pi;32 else33 r = r, 1b0;34 35assign so = r3;36 37endmodule33行r = r, 1b0;用Verilog實現shift register有很多種方式，但以33行這種方式最精簡，其他coding style可參考(筆記) 如何將值delay n個clock? (SOC) (Verilog)。Testbenchp2s_tb.v / Verilog 1/*2(C) OOMusou 2009 34Filename : p2s_tb.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Description : parallel in serial out testbench7Release : Oct/24/2009 1.08*/910timescale 1ns/1ns11includep2s.v1213module p2s_tb;1415reg clk;16reg rst_n;17reg load;18reg 3:0 pi;19wire so;2021initialbegin22 load =1b0;23 pi =4h0;24 #10;25 load =1b1;26 pi =4b1010;27 #20;28 load =1b0;29 pi =4h0;30end3132initial clk =1b0;33always #10 clk =clk;3435initialbegin36 rst_n =1b0;37 #5;38 rst_n =1b1;39end4041initialbegin42 $fsdbDumpfile(p2s.fsdb);43 $fsdbDumpvars(0, p2s_tb);44 #150;45 $finish;46end4748p2s p2s_0 (49 .clk(clk),50 .rst_n(rst_n),51 .load(load),52 .pi(pi),53 .so(so)54);5556endmodule模擬結果 串進並出 (Serial In Parallel Out) serial data依序送進shift register，當en為1時，一次將shift register內的資料送進parallel out。s2p.v / Verilog1/*2(C) OOMusou 2009 34Filename : s2p.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Synthesizer : Quartus II 7.27Description : serial in parallel out rtl8Release : Oct/24/2009 1.09*/1011module s2p (12 clk,13 rst_n,14 en,15 si,16 po17);1819input clk;20input rst_n;21input en;22input si;23output 3:0 po;2425reg 3:0 r;2627always(posedge clk ornegedge rst_n) 28 if (rst_n)29 r =8h0;30 else31 r = r, si;32 33assign po = (en) ? r : 4h0;34 35endmoduleTestbenchs2p_tb.v / Verilog1/*2(C) OOMusou 2009 34Filename : p2s_tb.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Description : serial in parallel out testbench7Release : Oct/24/2009 1.08*/910timescale 1ns/1ns11includes2p.v1213module s2p_tb;1415reg clk;16reg rst_n;17reg en;18reg si;19wire 3:0 po;2021initialbegin22 en =1b0;23 si =1b0;24 #10;25 / 4b101026 si =1b1;27 #20;28 si =1b0;29 #20;30 si =1b1;31 #20;32 en =1b1;33 si =1b0;34 #20;35 en =1b0;36 si =1b0;37end3839initial clk =1b0;40always #10 clk =clk;4142initialbegin43 rst_n =1b0;44 #5;45 rst_n =1b1;46end4748initialbegin49 $fsdbDumpfile(s2p.fsdb);50 $fsdbDumpvars(0, s2p_tb);51 #200;52 $finish;53end5455s2p s2p_0 (56 .clk(clk),57 .rst_n(rst_n),58 .en(en),59 .si(si),60 .po(po)61);6263endmodule模擬結果 串進串出 (Serial In Serial Out)基本上串進串出沒有任何實用功能，只能當成delay n個clk用，與(筆記) 如何將值delay n個clock? (SOC) (Verilog)一樣，只是在此順便提及。s2s.v / Verilog1/*2(C) OOMusou 2009 34Filename : s2p.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Synthesizer : Quartus II 7.27Description : serial in serial out rtl8Release : Oct/24/2009 1.09*/1011module s2s (12 clk,13 rst_n,14 si,15 so16);1718input clk;19input rst_n;20input si;21output so;2223reg 3:0 r;2425always(posedge clk ornegedge rst_n) 26 if (rst_n)27 r =8h0;28 else29 r = r, si;30 31assign so = r3;32 33endmoduleTestbenchs2s_tb.v/ Verilog1/*2(C) OOMusou 2009 34Filename : s2s_tb.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Description : serial in serial out testbench7Release : Oct/24/2009 1.08*/910timescale 1ns/1ns11includes2s.v1213module s2s_tb;1415reg clk;16reg rst_n;17reg si;18wire so;1920initialbegin21 si =1b0;22 #10;23 / 4b101024 si =1b1;25 #20;26 si =1b0;27 #20;28 si =1b0;29 #20;30 si =1b1;31end3233initial clk =1b0;34always #10 clk =clk;3536initialbegin37 rst_n =1b0;38 #5;39 rst_n =1b1;40end4142initialbegin43 $fsdbDumpfile(s2s.fsdb);44 $fsdbDumpvars(0, s2s_tb);45 #200;46 $finish;47end4849s2s s2s_0 (50 .clk(clk),51 .rst_n(rst_n),52 .si(si),53 .so(so)54);5556endmodule模擬結果 並進並出 (Parallel In Parallel Out)並進並出也沒實用功能，只是順便提及。p2p.v / Verilog1/*2(C) OOMusou 2009 34Filename : p2p.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Synthesizer : Quartus II 7.27Description : parallel in parallel out rtl8Release : Oct/24/2009 1.09*/1011module p2p (12 clk,13 rst_n,14 pi,15 po16);1718input clk;19input rst_n;20input 3:0 pi;21output 3:0 po;2223reg 3:0 r;2425always(posedge clk ornegedge rst_n) 26 if (rst_n)27 r =8h0;28 else29 r = pi;30 31assign po = r;32 33endmoduleTestbenchp2p_tb.v / Verilog1/*2(C) OOMusou 2009 34Filename : p2p_tb.v5Simulator : NC-Verilog 5.4 + Debussy 5.4 v96Description : parallel in parallel out testbench7Release : Oct/24/2009 1.08*/910timescale 1ns/1ns11includep2p.v1213module p2p_tb;1415reg clk;16reg rst_n;17reg 3:0 pi;18wire 3:0 po;1920initialbegin21 pi =4h0;22 #10;23 pi =4b1010;24 #20;25 pi =4b1100;26 #2027 pi =4h0;28end2930initial clk =1b0;31always #10 clk =clk;3233initialbegin34 rst_n =1b0;35 #5;36 rst_n =1b1;37end3839initialbegin40 $fsdbDu