[工学]THCII-1创新SOPC实验套件实 验 教 材.doc

THCII-1 创新SOPC实验套件实 验 教 材清华大学电子工程系清华大学科教仪器厂中 电 网ALTERA公司2006年THCII-1创新SOPC实验套件实验教材第一章 套件简介 主要技术指标1 本系统主要采用Altera公司的CycloneII系列 的EP2C5T144C8。2 核心板采用1M16bit的flash，256K16bit的Sram，可以支持NiosII系列实验。3 采用的串行配置器件包括EPCS1，同时支持AS和JTAG的下载方式。支持NiosII软核嵌入式处理器。4 提供的实验资源包括：a、1个7段数码管b、7个LEDc、4个轻触按键d、256色标准VGA彩显接口e、1个PS/2鼠标/键盘接口f、1个RS232接口。各个模块位置如图1-1所示：232串口VGA接口7段数码管PS2接口SRAMFLASHJTAG下载口AS下载口串行配置芯片7个LED4个按键RESET电源指示电源接口FPGA图1-1声明：对于使用过程中带电插拔以及不按照下述要求设置不用的管脚造成实验设备损坏的，厂家不予保修。第二章 实验平台使用说明封面照片为实验套件连接显示器、键盘，串口线等外围设备实验的效果图，其中显示器显示的为计数值，数字下方的方块为二进制值，下面对各模块进行说明。各模块说明如下：一、7段数码管图2-1信号名称对应FPGA引脚LED_a144LED_b142LED_c3LED_d7LED_e9LED_f4LED_g8LED_dp143数码管为共阴，要使某个数码管点亮，必须使相应的译码输出为高 数字不带小数点译码dp g f e d c b a带小数点译码dp a b c d e f g00011111110111111100000110100001102010110111101101130100111111001111401100110111001105011011011110110160111110111111101700000111100001118011111111111111190110111111101111A0111011111110111B0111110011111100C0011100110111001D0101111011011110E0111100111111001F0111000111110001二、VGA接口图2-2信号名称对应FPGA引脚VGA_R0141VGA_R1139VGA_R2137VGA_G0136VGA_G1135VGA_G2134VGA_B0133VGA_B1132v_sync129h_sync126三、232串口图2-3信号名称对应FPGA引脚RXD125TXD122四、PS2接口图2-4信号名称对应FPGA引脚PS_DATA120PS_CLK121五、LED图2-5信号名称对应FPGA引脚LD1119LD2118LD3115LD4114LD5113LD6112LD7104六、按键图2-6信号名称对应FPGA引脚PSW1103PSW2101PSW3100PSW499七、系统复位、时钟时钟、复位模块CLK88RESET97八、SRAM、flash模块 图2-7存储器模块信号名称对应FPGA引脚信号名称对应FPGA引脚addr0不用指定data094addr159data193addr258data292addr357data387addr455data486addr553data581addr652data680addr751data779addr848data860addr947data963addr1045data1064addr1144data1165addr1243data1267addr1342data1369addr1432data1470addr1540data1571addr1641sram_ce_n96addr1731sram_oe_n74addr1827sram_we_n75addr1928flash_ce_n25addr2030flash_oe_n24sram_be072flash_we_n26sram_be173注：FLASH为1M X 16，sopc的地址按字节计算，因此地址线为21位，如果按照16位计算，地址线只须20位，而最低位不用接线。九、使用设备须知对实验板上的接口进行操作应该在拔掉电源线后进行。对实验中不用的管脚一律设置为输入三态，具体设置步骤为：Assignments-Devices，如图2-8所示图2-8点击Device & Pin Options，如图2-9所示，在图2-9中选Unused Pins ，Reserve all unused pins设置为As input tri-stated如图2-9所示。图2-9第三章 EDA实验实验一 VGA计数实验一、实验说明本实验由RESET健清0，PSW1健控制预制数，按下置入1234，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值，编辑源程序，观察实验结果。二、设计输入Quartus II的工作界面如图3-1-1所示。图3-1-11 新建一个工程（1） 单击菜单FileNew Project Wizard,如果是首次使用将弹出新建工程向导介绍（Introduction）对话框。从对话框中可以了解到新建工程向导中将要完成的工作内容和一些其他信息。（2） 单击Next进入工程建立路径和工程名称对话框，如图3-1-2所示。在第一栏中设定好工程建立的路径，在第二栏中填写工程的名称，在第三栏中填写工程顶层设计文件的名称。在默认状态下，顶层设计文件的名称和工程名称相同。图3-1-2（3） 单击Next进入加入工程文件对话框。如图3-1-3所示。由于本例所建立的工程没有可以使用的文件，所以不需要做任何操作。图3-1-3（4） 单击Next进入目标器件选择对话框。如图3-1-4所示。在这里还可以选择目标器件的参数，有器件的封装型号，引出端数目和速度级别。图3-1-4（5） 单击Next指定工程中应用的其它EDA工具，如图3-1-5所示。图3-1-5（6） 单击Next可以看到新建工程的报告，所设置的参数都在报告中，单击Finish完成新工程的建立。2 使用HDL语言输入选择FileNew，选择VHDL File，如图3-1-6所示。单击ok，弹出HDL编辑窗口，如图3-1-6所示。图3-1-6在HDL编辑窗口中输入下面的代码。输入好代码后，单击工具栏上的按钮，在弹出的对话框中键入文件名后单击保存即可。3 源代码如下顶层文件源代码如下所示：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity count_top is Port ( rst : in std_logic; clkin : in std_logic; ld : in std_logic; up : in std_logic; hs : out std_logic; vs : out std_logic; r : out std_logic_vector(2 downto 0); g : out std_logic_vector(2 downto 0); b : out std_logic_vector(1 downto 0);end count_top;architecture Behavioral of count_top iscomponent counterport(CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in STD_LOGIC_VECTOR(15 downto 0); COUNT: inout STD_LOGIC_VECTOR(15 downto 0);end component;component HEX2LED_4 Port ( HEX : in std_logic_vector(15 downto 0); LED1 : out std_logic_vector(6 downto 0); LED2 : out std_logic_vector(6 downto 0); LED3 : out std_logic_vector(6 downto 0); LED4 : out std_logic_vector(6 downto 0);end component;component vga_16 Port ( clk : in std_logic; hs : out std_logic; vs : out std_logic; r : out std_logic; g : out std_logic; b : out std_logic; innum : in std_logic_vector(15 downto 0); innum0 : in std_logic_vector(15 downto 0); innum1 : in std_logic_vector(6 downto 0); innum2 : in std_logic_vector(6 downto 0); innum3 : in std_logic_vector(6 downto 0); innum4 : in std_logic_vector(6 downto 0);end component;signal clk: std_logic;signal N: std_logic_vector(23 downto 0);signal do: std_logic_vector(15 downto 0);signal din: std_logic_vector(15 downto 0);signal ce: std_logic;signal vga_r,vga_g,vga_b: std_logic;signal HEX : std_logic_vector(15 downto 0);signal LED1 : std_logic_vector(6 downto 0);signal LED2 : std_logic_vector(6 downto 0);signal LED3 : std_logic_vector(6 downto 0);signal LED4 : std_logic_vector(6 downto 0);beginprocess(clkin, N)beginif (clkinevent and clkin=1) thenN=N+1;end if;end process;clk=N(23);din=0001001000110100;ce=1;U1: counter port map(clk,rst,ce,ld,up,din,do);U2: HEX2LED_4 port map(do, led1,led2,led3,led4);U3:vga_16 port map(clkin,hs,vs,vga_r,vga_g,vga_b,do,do,led1,led2,led3,led4);r(0) = vga_r;r(1) = vga_r;r(2) = vga_r;g(0) = vga_g;g(1) = vga_g;g(2) = vga_g;b(0) = vga_b;b(1) = vga_b;end Behavioral;计数器源程序如下所示：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter isport(CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in STD_LOGIC_VECTOR(15 downto 0); COUNT: inout STD_LOGIC_VECTOR(15 downto 0);end counter;architecture Behavioral of counter isbeginprocess (CLK, RESET) begin if RESET=0 then COUNT 0); elsif CLK=1 and CLKevent then if CE=1 then if LOAD=0 then COUNT = DIN; else if DIR=1 then COUNT = COUNT + 1; else COUNT = COUNT - 1; end if; end if; end if; end if;end process; end Behavioral;数码管译码源程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity HEX2LED_4 is Port ( HEX : in std_logic_vector(15 downto 0); LED1 : out std_logic_vector(6 downto 0); LED2 : out std_logic_vector(6 downto 0); LED3 : out std_logic_vector(6 downto 0); LED4 : out std_logic_vector(6 downto 0);end HEX2LED_4;architecture Behavioral of HEX2LED_4 isbegin -HEX-to-seven-segment decoder- HEX: in STD_LOGIC_VECTOR (3 downto 0);- LED: out STD_LOGIC_VECTOR (6 downto 0);- - segment encoding- 0- - - 5 | | 1- - - 6- 4 | | 2- - 3 with HEX(3 downto 0) SELect LED1= 1111001 when 0001, -1 0100100 when 0010, -2 0110000 when 0011, -3 0011001 when 0100, -4 0010010 when 0101, -5 0000010 when 0110, -6 1111000 when 0111, -7 0000000 when 1000, -8 0010000 when 1001, -9 0001000 when 1010, -A 0000011 when 1011, -b 1000110 when 1100, -C 0100001 when 1101, -d 0000110 when 1110, -E 0001110 when 1111, -F 1000000 when others; -0 with HEX(7 downto 4) SELect LED2= 1111001 when 0001, -1 0100100 when 0010, -2 0110000 when 0011, -3 0011001 when 0100, -4 0010010 when 0101, -5 0000010 when 0110, -6 1111000 when 0111, -7 0000000 when 1000, -8 0010000 when 1001, -9 0001000 when 1010, -A 0000011 when 1011, -b 1000110 when 1100, -C 0100001 when 1101, -d 0000110 when 1110, -E 0001110 when 1111, -F 1000000 when others; -0with HEX(11 downto 8) SELect LED3= 1111001 when 0001, -1 0100100 when 0010, -2 0110000 when 0011, -3 0011001 when 0100, -4 0010010 when 0101, -5 0000010 when 0110, -6 1111000 when 0111, -7 0000000 when 1000, -8 0010000 when 1001, -9 0001000 when 1010, -A 0000011 when 1011, -b 1000110 when 1100, -C 0100001 when 1101, -d 0000110 when 1110, -E 0001110 when 1111, -F 1000000 when others; -0with HEX(15 downto 12) SELect LED4= 1111001 when 0001, -1 0100100 when 0010, -2 0110000 when 0011, -3 0011001 when 0100, -4 0010010 when 0101, -5 0000010 when 0110, -6 1111000 when 0111, -7 0000000 when 1000, -8 0010000 when 1001, -9 0001000 when 1010, -A 0000011 when 1011, -b 1000110 when 1100, -C 0100001 when 1101, -d 0000110 when 1110, -E 0001110 when 1111, -F 1000000 when others; -0end Behavioral;VGA显示源程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity vga_16 is Port ( clk : in std_logic; hs : out std_logic; vs : out std_logic; r : out std_logic; g : out std_logic; b : out std_logic; innum : in std_logic_vector(15 downto 0); innum0 : in std_logic_vector(15 downto 0); innum1 : in std_logic_vector(6 downto 0); innum2 : in std_logic_vector(6 downto 0); innum3 : in std_logic_vector(6 downto 0); innum4 : in std_logic_vector(6 downto 0);end vga_16;architecture Behavioral of vga_16 isconstant color1: std_logic_vector:=010;-显示颜色为红色constant color2: std_logic_vector:=100;constant color3: std_logic_vector:=001;constant color4: std_logic_vector:=110;signal hs1,vs1,fclk,cclk: std_logic;signal fs: std_logic_vector(5 downto 0);signal cc: std_logic_vector(4 downto 0);signal ll: std_logic_vector(8 downto 0);signal rgbp: std_logic_vector(3 downto 1);signalrgb: std_logic_vector(3 downto 1);beginrgb(1)=rgbp(1) and hs1 and vs1;rgb(2)=rgbp(2) and hs1 and vs1;rgb(3)=rgbp(3) and hs1 and vs1;fclk=fs(5);cclk=cc(4);hs=hs1;vs=vs1;r=rgb(2);g=rgb(3);b=rgb(1);process(clk)beginif clkevent and clk=1 thenif fs=50 thenfs=000000;elsefs=fs+1;end if;end if;end process;process(fclk)beginif fclkevent and fclk=1 thenif cc=27 thencc=00000;elsecc=cc+1;end if;end if;end process;process(cclk)beginif cclkevent and cclk=1 thenif ll=481 thenll=000000000;elsell23 then -行同步hs1=0;else hs1479 then-场同步vs1=0;else vs12 and cc60 and ll101 and innum4(0)=0 then-a0rgbp180 and ll221 and innum4(6)=0 then-g0rgbp300 and ll341 and innum4(3)=0 then-d0rgbp60 and ll2 and cc4) and innum4(5)=0 then-f0rgbp5 and cc7) and innum4(1)=0 then-b0rgbp=color1;else rgbp201 and ll2 and cc4) and innum4(4)=0 then-e0rgbp5 and cc7) and innum4(2)=0 then-c0rgbp=color1;else rgbp350 and ll2 and cc4 and innum(15)=1 then-p8rgbp3 and cc5 and innum(14)=1 then-p4rgbp4 and cc6 and innum(13)=1 then-p2rgbp5 and cc7 and innum(12)=1 then-p1rgbp=color1;else rgbp380 and ll2 and cc4 and innum0(15)=1 then-q8rgbp3 and cc5 and innum0(14)=1 then-q4rgbp4 and cc6 and innum0(13)=1 then-q2rgbp5 and cc7 and innum0(12)=1 then-q1rgbp=color1;else rgbp=000;end if;elsergbp7 and cc60 and ll101 and innum3(0)=0 thenrgbp180 and ll221 and innum3(6)=0 thenrgbp300 and ll341 and innum3(3)=0 thenrgbp60 and ll7 and cc9) and innum3(5)=0 thenrgbp10 and cc12) and innum3(1)=0 thenrgbp=color2;else rgbp201 and ll7 and cc9) and innum3(4)=0 thenrgbp10 and cc12) and innum3(2)=0 thenrgbp=color2;else rgbp350 and ll7 and cc9 and innum(11)=1 thenrgbp8 and cc10 and innum(10)=1 thenrgbp9 and cc11 and innum(9)=1 thenrgbp10 and cc12 and innum(8)=1 thenrgbp=color2;else rgbp380 and ll7 and cc9 and innum0(11)=1 thenrgbp8 and cc10 and innum0(10)=1 thenrgbp9 and cc11 and innum0(9)=1 thenrgbp10 and cc12 and innum0(8)=1 thenrgbp=color2;else rgbp=000;end if;elsergbp12 and cc60 and ll101 and innum2(0)=0 thenrgbp180 and ll221 and innum2(6)=0 thenrgbp300 and ll341 and innum2(3)=0 thenrgbp60 and ll12 and cc14) and innum2(5)=0 thenrgbp15 and cc17) and innum2(1)=0 thenrgbp=color3;else rgbp201 and ll12 and cc14) and innum2(4)=0 thenrgbp15 and cc17) and innum2(2)=0 thenrgbp=color3;else rgbp350 and ll12 and cc14 and innum(7)=1 thenrgbp13 and cc15 and innum(6)=1 thenrgbp14 and cc16 and innum(5)=1 thenrgbp15 and cc17 and innum(4)=1 thenrgbp=color3;else rgbp380 and ll12 and cc14 and innum0(7)=1 thenrgbp13 and cc15 and innum0(6)=1 thenrgbp14 and cc16 and innum0(5)=1 thenrgbp15 and cc17 and innum0(4)=1 thenrgbp=color3;else rgbp=000;end if;elsergbp17 and cc60 and ll101 and innum1(0)=0 thenrgbp180 and ll221 and innum1(6)=0 thenrgbp300 and ll341 and innum1(3)=0 thenrgbp60 and ll17 and cc19) and innum1(5)=0 thenrgbp20 and cc22) and innum1(1)=0 thenrgbp=color4;else rgbp201 and ll17 and cc19) and innum1(4)=0 thenrgbp20 and cc22) and innum1(2)=0 thenrgbp=color4;else rgbp350 and ll17 and cc19 and innum(3)=1 thenrgbp18 and cc20 and innum(2)=1 thenrgbp19 and cc21 and innum(1)=1 thenrgbp20 and cc22 and innum(0)=1 thenrgbp=color4;else rgbp380 and ll17 and cc19 and innum0(3)=1 thenrgbp18 and cc20 and innum0(2)=1 thenrgbp19 and cc21 and innum0(1)=1 thenrgbp20 and cc22 and innum0(0)=1 thenrgbp=color4;else rgbp=000;end if;else rgbp=000;end if;else rgbp=000;end if;end process;end Behavioral;三、编译与下载（1）进行编译 选择菜单ProcessingStart Compilation或者单击工具栏上的按钮，编译器马上开始编译设计。在编译过程中，状态窗口中会显示编译的进度，信息窗口中会显示编译进行的信息。如图3-1-7所示。图3-1-7（2）绑定引脚 选择菜单AssignmentsPins，如图3-1-8所示，在location位置输入相应的管脚号，然后保存，重新编译。图3-1-8（3