ALTERA nco IP核用户手册.pdf

101 Innovation Drive San Jose, CA 95134 UG-NCOCOMPILER-13.0 User Guide NCO MegaCore Function Feedback Subscribe NCO MegaCore Function User Guide 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. November 2013Altera CorporationNCO MegaCore Function User Guide ISO 9001:2008 Registered November 2013Altera CorporationNCO MegaCore Function User Guide Contents Chapter 1. About This MegaCore Function Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 2. Getting Started Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DSP Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Parameterize the MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Generate the MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Simulating the Design in ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Compile the Design and Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Chapter 3. Parameter Settings Setting Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chapter 4. Functional Description Numerically Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Spectral Purity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Avalon-ST and Avalon-MM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Large ROM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Small ROM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CORDIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Multiplier-Based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Phase Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Phase Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Multi-Channel NCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Frequency Hopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Appendix A. Example Multichannel Design Multichannel Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A1 Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A3 ivContents NCO MegaCore FunctionNovember 2013Altera Corporation User Guide Implementation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A4 Simulation Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A4 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info2 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info2 November 2013Altera CorporationNCO MegaCore Function User Guide 1. About This MegaCore Function This document describes the Altera NCO MegaCore function. The Altera NCO MegaCore function generates numerically controlled oscillators (NCOs) customized for Altera devices. You can use the IP Toolbench interface to implement a variety of NCO architectures, including ROM-based, CORDIC-based, and multiplier-based. IP Toolbench also includes time and frequency domain graphs that dynamically display the functionality of the NCO, based on your parameter settings. A numerically controlled oscillator synthesizes a discrete-time, discrete-valued representation of a sinusoidal waveform. Designers typically use NCOs in communication systems. In such systems, they are used as quadrature carrier generators in I-Q mixers, in which baseband data is modulated onto the orthogonal carriers in one of a variety of ways. Figure 11 shows an NCO used in a simple modulator system. Designers also use NCOs in all-digital phase-locked-loops for carrier synchronization in communications receivers, or as standalone frequency shift keying (FSK) or phase shift keying (PSK) modulators. In these applications, the phase or the frequency of the output waveform varies directly according to an input data stream. Features The Altera NCO MegaCore function supports the following features: Supports 32-bit precision for angle and magnitude Source interface is compatible with the Avalon Interface Specification IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators Figure 11. Simple Modulator Constellation Mapper IF Signal NCO Q I FIR Filter FIR Filter cos(wt) sin(wt) 12Chapter 1: About This MegaCore Function Release Information NCO MegaCore FunctionNovember 2013Altera Corporation User Guide Supports multiple NCO architectures: Multiplier-based implementation using DSP blocks or logic elements (LEs), (single cycle and multi-cycle) Parallel or serial CORDIC-based implementation ROM-based implementation using embedded array blocks (EABs), embedded system blocks (ESBs), or external ROM Supports single or dual outputs (sine/cosine) Allows variable width frequency modulation input Allows variable width phase modulation input Supports user-defined frequency resolution, angular precision, and magnitude precision Supports frequency hopping Supports multichannel capability Generates simulation files and architecture-specific testbenches for VHDL, Verilog HDL and MATLAB Includes dual-output oscillator and quaternary frequency shift keying (QFSK) modulator example designs Easy-to-use IP Toolbench interface Release Information Table 11 provides information about this release of the Altera NCO MegaCore function. fFor more information about this release, refer to the MegaCore IP Library Release Notes and Errata. Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function. The MegaCore IP Library Release Notes and Errata report any exceptions to this verification. Altera does not verify compilation with MegaCore function versions older than one release. Device Family Support Altera offers the following device support levels for Altera IP cores: Table 11. NCO MegaCore Function Release Information ItemDescription Version12.1 Release DateNovember 2012 Ordering CodeIP-NCO Product ID(s)0014 Vendor ID(s)6AF7 Chapter 1: About This MegaCore Function13 MegaCore Verification November 2013Altera CorporationNCO MegaCore Function User Guide Preliminary supportAltera verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution. Final supportAltera verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. Table 13 shows the level of support offered by the NCO MegaCore function to each of the Altera device families. MegaCore Verification Before releasing a version of the NCO MegaCore function, Altera runs comprehensive regression tests to verify its quality and correctness. First a custom variation of the NCO MegaCore function is created. Next, Verilog HDL and VHDL IP functional simulation models are exercised by their appropriate testbenches in ModelSim simulators and the results are compared to the output of a bit-accurate model. The regression suite covers various parameters such as architecture options, frequency modulation, phase modulation, and precision. Table 12. Device Family Support Device FamilySupport Arria II GXFinal Arria II GZFinal Arria VFull Cyclone IIIFinal Cyclone III LSFinal Cyclone IVFinal Stratix IIIFinal Stratix IV GTFinal Stratix IV GX/EFinal Stratix VFull Other device familiesNo support 14Chapter 1: About This MegaCore Function Performance and Resource Utilization NCO MegaCore FunctionNovember 2013Altera Corporation User Guide Figure 12 shows the regression flow. Performance and Resource Utilization This section shows typical expected performance for a NCO MegaCore function using the Quartus II software and a target fMAX set to 1GHz with Cyclone III and Stratix IV devices. 1Cyclone III devices use combinational look-up tables (LUTs) and logic registers; Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic registers. It may be possible to significantly reduce memory utilization by setting a lower target fMAX. Table 14 shows performance figures for Cyclone III devices. Figure 12. Regression Flow NCO Compiler Wizard Bit Accurate Model Output File Verilog HDL Output File VHDL Output File Synthesis Structure Output File Perl Script Parameter Sweep Compare Results Testbench All Languages Table 13. NCO MegaCore Function PerformanceCyclone III Devices Accumulator Width Angular Precision Magnitude Precision Combinational LUTs Logic Registers Memory 99 Blocks fMAX (MHz) BitsM9K Large ROM (1) 32121215614998,30412336 Multiplier-Based (1) Chapter 1: About This MegaCore Function15 Installation and Licensing November 2013Altera CorporationNCO MegaCore Function User Guide Table 15 shows performance figures for Stratix IV devices. Installation and Licensing The NCO MegaCore Function is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website, . fFor system requirements and installation instructions, refer to the Altera Software Installation and Licensing manual. Figure 13 shows the directory structure after you install the NCO MegaCore Function, where is the installation directory for the Quartus II software. 32161632124012,28828212 Parallel CORDIC (1) 3214141,1731,158335 Small ROM (1) 32141636329861,4408320 Notes to Table 14: (1)Using EP3C10F256C6 devices. Table 13. NCO MegaCore Function PerformanceCyclone III Devices Accumulator Width Angular Precision Magnitude Precision Combinational LUTs Logic Registers Memory 99 Blocks fMAX (MHz) BitsM9K Table 14. NCO MegaCore Function PerformanceStratix IV Devices Accumulator Width Angular Precision Magnitude Precision Combinational ALUTs Logic Registers Memory 1818 Blocks fMAX (MHz) BitsM9K Large ROM (1) 3212126914998,30412653 Multiplier-Based (1) 32161611720612,28824467 Parallel CORDIC (1) 3214141,3701,536591 Small ROM (1) 32141618929861,4408612 Note to Table 15: (1)Using EP4SGX70DF29C2X devices. 16Chapter 1: About This MegaCore Function Installation and Licensing NCO MegaCore FunctionNovember 2013Altera Corporation User Guide The default installation directory on Windows is c:altera; or on Linux is /opt/altera. OpenCore Plus Evaluation With Alteras free OpenCore Plus evaluation feature, you can perform the following actions: Simulate the behavior of a megafunction (Altera MegaCore function or AMPPSM megafunction) within your system. Verify the functionality of your design, as well as evaluate its size and speed quickly and easily. Generate time-limited device programming files for designs that include megafunctions. Program a device and verify your design in hardware. You only need to purchase a license for the NCO MegaCore function when you are completely satisfied with its functionality and performance, and want to take your design to production. After you purchase a license, you can request a license file from the Altera website at and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. fFor more information about OpenCore Plus hardware evaluation, refer to AN 320: OpenCore Plus Evaluation of Megafunctions. OpenCore Plus Time-Out Behavior OpenCore Plus hardware evaluation supports the following operation modes: Untetheredthe design runs for a limited time. Figure 13. Directory Structure lib Contains encrypted lower-level design files. ip Contains the Altera MegaCore IP Library and third-party IP cores. Installation directory. altera Contains the Altera MegaCore IP Library. common Contains shared components. nco Contains the NCO MegaCore function files. example_designs Contains example designs. multi_channel Contains the multichannel design. Chapter 1: About This MegaCore Function17 Installation and Licensing November 2013Altera CorporationNCO MegaCore Function User Guide Tetheredrequires a connection between your board and the host computer. If tethered mode is supported by all megafunctions