ds_nios2_3c25_lcd电子信息外文资料翻译原件.pdf

March 2009 Altera CorporationNios II 3C25 Microprocessor with LCD Controller Data Sheet DS-01003-1.1 March 2009 Nios II 3C25 Microprocessor with LCD Controller Data Sheet Introduction This data sheet describes a single instance of a Nios II-based processor system with a built-in LCD controller targeted for an Altera Cyclone III 3C25F324 FPGA on the Altera Nios II Embedded Evaluation Kit, Cyclone III Edition. The Nios II 3C25 Microprocessor with LCD Controller is a complete system-on-a-programmable-chip (SOPC) solution that incorporates a rich set of system peripherals and standard interfaces for a wide range of embedded applications involving video processing and LCD touch panel control. The key benefit of implementing a processor system in an FPGA is that you can customize your system using intellectual property (IP) cores, custom logic, and hardware acceleration to optimize to your target application. Nearly every feature in the system is available for you to configure, customize, duplicate, or remove easily. You can further enhance your system by adding additional IP to the Cyclone III 3C25 device, or you can remove IP or select options that reduce logic utilization allowing you to port to a smaller device to reduce cost. 1Although this data sheet describes a system targeted for the Cyclone III 3C25 FPGA device, the data sheet also shows you how to configure the processor system for another Altera FPGA device and hardware platform of your choice. Features The following list summarizes the main features of the Nios II 3C25 microprocessor with LCD controller. Target Hardware Board Altera Nios II Embedded Evaluation Kit, Cyclone III Edition Device System name: cycloneIII_3c25_niosII_video Family: Cyclone III Device: 3C25F324 Total logic elements (LE) used: 22,875 / 24,624 (93%) Total pins used: 167 / 216 (77%) Total memory used: 163,270 / 608,256 (27%) Processor Nios II/f processor core Nominal metrics: 113 DMIPS at 100 MHz, 1,4001,800 LEs, MMU/MPU option disabled 4-KByte instruction cache, 2-KByte data cache Page 2Introduction Nios II 3C25 Microprocessor with LCD Controller Data Sheet March 2009 Altera Corporation JTAG debug module for downloading software, 300400 LEs Memory Interfaces Common flash interface (CFI) flash memory 16 MBytes High performance DDR SDRAM memory Nominal frequency: 133 MHz, 16 bits, 32 MBytes SD/MMC card serial peripheral interface (SPI) 20-MHz SPI interface clock frequency Supports up to 1-Gbit SD card memory Synchronous SRAM memory 1 MByte Communication Interfaces Ethernet MAC 10/100/1000 Base T Integrated in receive and transmit FIFO 512 32 bits each Media independent interface (MII)/gigabit media independent interface (GMII) support 32-bit transmit and receive scatter gather direct memory access (SG-DMA) channels JTAG UART with integrated read and write FIFO UART for RS-232 serial communication 115,200 baud rate, no parity, 8 data bits, 1 stop bit 2-wire interface Implemented using general purpose PIOs Dedicated to LCD controller interface Video Subsystem Integrated LCD controller IP Configured to 800 480 resolution Interface for LCD control using 2-wire interface Implemented using general purpose PIOs Integrated touch panel controller IP Interfaces to LCD using 3-wire SPI Master mode 8 bit data register, 32 KHz DescriptionPage 3 March 2009 Altera CorporationNios II 3C25 Microprocessor with LCD Controller Data Sheet Video pipeline Streaming video data path Video frame buffer RGB Sync generation IP 128-byte dual clock FIFO System Peripherals Timers/counters System clock timer 32-bit counter size, 10-ms time-out period High resolution timer 32-bit counter size, 10-s time-out period Performance counter 1 simultaneous measured section 4 button PIOs (input only) 2 LED PIOs (output only) System ID Cyclone III remote update controller configuration peripheral Description The Nios II 3C25 microprocessor with LCD controller incorporates a Nios II processor, LCD controller, memories, a video pipeline, and more in a single Cyclone III 3C25 FPGA. You can configure nearly every aspect of the processor system to suit your application requirements. You can configure the Nios II processor as one of following cores: A size-optimized economy (/e) core A performance-optimum fast (/f) core An optimum size-to-performance standard (/s) core In addition, the fast core comes with options to include a memory management unit (MMU) as well as various precise exceptions and memory protection features. The Nios II processor supports custom instructions allowing you to implement software functions in hardware to increase system performance. You can configure the JTAG debug module to support hardware breakpoints, data triggers, and instruction and data on-chip and off-chip trace. The microprocessor supports an LCD color touch panel by integrating the LCD controller hardware, which has been implemented as part of a video pipeline. The video pipeline is fully logic based, composed of IP cores you can modify to suit any resolution or aspect ratio. Page 4Description Nios II 3C25 Microprocessor with LCD Controller Data Sheet March 2009 Altera Corporation A DDR SDRAM memory interface holds the video buffer. A 1-MByte SSRAM memory is available for processor program code. For code larger than 1 MByte, the DDR SDRAM memory can also hold processor program code. User-selectable SRAM memory (on-chip) holds the DMA descriptors. A CFI flash controller supports flash memory to store application code and FPGA configuration data. The microprocessor integrates an SD/MMC controller that is SD card compliant. The system also includes a 10/100/1000 Ethernet MAC with SG-DMA channels for network access. Figure 1 shows the functional blocks of the Nios II 3C25 microprocessor with LCD controller system. Table 1 lists the pin definitions and signal descriptions. In the Location column, letter values refer to the pin row within the FPGA and numeric values refer to the pin column. So for example, A1 denotes the pin located in row A and column 1. Figure 1. Block Diagram Notes to Figure 1 (1)The SSRAM controller shares the address and data buses with the flash interface. (2)The LCD panel interface shares the clock signal with the touch panel ADC interface. 10/100 Ethernet MAC JTAG Debug Mode Nios II /f Core Data Cache Instruction CacheTX SG DMA RX SG DMA Slow Peripheral BridgeClock Crossing Bridge SG DMA FIFO Video Pipeline Performance Counter PLL High Resolution Timer LCD Panel Interface System Timer System ID Touch Panel ADC Interface SSRAM Controller Pipelined Bridge Tristate Bridge Flash Interface SD/MMC Card Interface Remote Update Controller UART EEPROM LED Button PIO CLK DATA0-31 ADDR0-23 ADSC_n BW_n0-3 BWE_n CE_n OE_n RESET_n OE_n CS_n WR_n ADDR0-23 DATA0-31 SD_CLK SD_CMD SD_DAT3 SD_DAT LED0-1 BUTTON0-3 CLK, CLK_n ADDR0-12 BA0-1 DATA0-15 DM0-1 DQS0-1 RAS_n CAS_n CS_n WE_n CKE DDR SDRAM Controller RESET_n CLK 50 SDA DATA0-7 CLK VD HD PENIRQ_n DEN DIN DOUT DCLK CS_n TXD RXD I2CSCL I2CDAT SCEN (2) DCLK MDC MDIO RX_CLK RX_COL RX_D0-3 RX_ERR TX_D0-3 TX_CLK TX_EN RESET_n RX_DV RX_CRS (1) DescriptionPage 5 March 2009 Altera CorporationNios II 3C25 Microprocessor with LCD Controller Data Sheet fFor the Cyclone III 3C25 device pin list, refer to Pin Information for the Cyclone III EP3C25 Device. Table 1. Signal Descriptions (Part 1 of 5) Pin Name Location Signal Description Direction I/O Standard System Clock and Reset Inputs top_clkin_50V950 MHz crystal oscillator inputInput2.5 V top_reset_nN2FPGA reset input (active low)Input2.5 V DDR SDRAM Memory (A2S56D40CTP-G5PP) Interface top_mem_addr0U1AddressOutputSSTL-2 Class I top_mem_addr1U5AddressOutputSSTL-2 Class I top_mem_addr2U7AddressOutputSSTL-2 Class I top_mem_addr3U8AddressOutputSSTL-2 Class I top_mem_addr4P8AddressOutputSSTL-2 Class I top_mem_addr5P7AddressOutputSSTL-2 Class I top_mem_addr6P6AddressOutputSSTL-2 Class I top_mem_addr7T14AddressOutputSSTL-2 Class I top_mem_addr8T13AddressOutputSSTL-2 Class I top_mem_addr9V13AddressOutputSSTL-2 Class I top_mem_addr10U17AddressOutputSSTL-2 Class I top_mem_addr11V17AddressOutputSSTL-2 Class I top_mem_addr12U16AddressOutputSSTL-2 Class I top_mem_ba0V11Bank addressOutputSSTL-2 Class I top_mem_ba1V12Bank addressOutputSSTL-2 Class I top_mem_cas_nT4CAS command (active low)OutputSSTL-2 Class I top_mem_ckeR13Clock enableOutputSSTL-2 Class I top_mem_clkU2Positive differential clock inputBidirectionalSSTL-2 Class I top_mem_clk_nV2Negative differential clock inputBidirectionalSSTL-2 Class I top_mem_cs_nV1Chip select input (active low)OutputSSTL-2 Class I top_mem_dm0V3Data maskOutputSSTL-2 Class I top_mem_dm1V8Data maskOutputSSTL-2 Class I top_mem_dq0U4Data I/OBidirectionalSSTL-2 Class I top_mem_dq1V4Data I/OBidirectionalSSTL-2 Class I top_mem_dq2R8Data I/OBidirectionalSSTL-2 Class I top_mem_dq3V5Data I/OBidirectionalSSTL-2 Class I top_mem_dq4P9Data I/OBidirectionalSSTL-2 Class I top_mem_dq5U6Data I/OBidirectionalSSTL-2 Class I top_mem_dq6V6Data I/OBidirectionalSSTL-2 Class I top_mem_dq7V7Data I/OBidirectionalSSTL-2 Class I top_mem_dq8U13Data I/OBidirectionalSSTL-2 Class I top_mem_dq9U12Data I/OBidirectionalSSTL-2 Class I Page 6Description Nios II 3C25 Microprocessor with LCD Controller Data Sheet March 2009 Altera Corporation top_mem_dq10U11Data I/OBidirectionalSSTL-2 Class I top_mem_dq11V15Data I/OBidirectionalSSTL-2 Class I top_mem_dq12U14Data I/OBidirectionalSSTL-2 Class I top_mem_dq13R11Data I/OBidirectionalSSTL-2 Class I top_mem_dq14P10Data I/OBidirectionalSSTL-2 Class I top_mem_dq15V14Data I/OBidirectionalSSTL-2 Class I top_mem_dqs0U3Data strobeBidirectionalSSTL-2 Class I top_mem_dqs1T8Data strobeBidirectionalSSTL-2 Class I top_mem_ras_nV16RAS command (active low)OutputSSTL-2 Class I top_mem_we_nU15Write enable command (active low)OutputSSTL-2 Class I Parallel Flash (PC28F256P30B85) and SSRAM (IS61LPS25636A-200TQL1) Memory Interface top_flash_cs_nE2Flash chip enable (active low)Output2.5 V top_flash_oe_nD17Flash output enable (active low)Output2.5 V top_flash_reset_nC3Flash reset (active low)Output2.5 V top_flash_ssram_a1E12Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a2A16Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a3B16Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a4A15Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a5B15Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a6A14Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a7B14Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a8A13Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a9B13Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a10A12Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a11B12Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a12A11Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a13B11Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a14C10Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a15D10Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a16E10Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a17C9Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a18D9Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a19A7Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a20A6Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a21B18Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a22C17Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_a23C18Flash and SSRAM shared addressOutput2.5 V top_flash_ssram_d0H3Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d1D1Flash and SSRAM shared dataBidirectional2.5 V Table 1. Signal Descriptions (Part 2 of 5) Pin Name Location Signal Description Direction I/O Standard DescriptionPage 7 March 2009 Altera CorporationNios II 3C25 Microprocessor with LCD Controller Data Sheet top_flash_ssram_d2A8Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d3B8Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d4B7Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d5C5Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d6E8Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d7A4Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d8B4Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d9E7Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d10A3Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d11B3Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d12D5Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d13B5Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d14A5Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d15B6Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d16C16Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d17D12Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d18E11Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d19D2Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d20E13Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d21E14Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d22A17Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d23D16Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d24C12Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d25A18Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d26F8Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d27D7Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d28F6Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d29E6Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d30G6Flash and SSRAM shared dataBidirectional2.5 V top_flash_ssram_d31C7Flash and SSRAM shared dataBidirectional2.5 V top_flash_wr_nD18Flash write enable (active low)Output2.5 V top_ssram_adsc_nF7SSRAM address status controller (active low) Output2.5 V top_ssram_bw_n0F10SSRAM byte write controls (active low)Output2.5 V top_ssram_bw_n1F11SSRAM byte write controls (active low)Output2.5 V top_ssram_bw_n2F12SSRAM byte write controls (active low)Output2.5 V top_ssram_bw_n3F13SSRAM byte write controls (active low)Output2.5 V top_ssram_bwe_nG13SSRAM byte write enable (active low)Output2.5 V top_ssram_ce_nF9SSRAM chip select (active low)Output2.5 V top_ssram_clkA2SSRAM clockOutput2.5 V Table 1. Signal Descriptions (Part 3 of 5) Pin Name Location Signal Description Direction I/O Standard Page 8Description Nios II 3C25 Microprocessor with LCD Controller Data Sheet March 2009 Altera Corporation top_ssram_oe_nE9SSRAM output enable (active low)Output2.5 V Touch Panel Analog to Digital Converter (AD7843) Interface top_HC_ADC_CS_NR5Chip select for ADC (active low)Output2.5 V top_HC_ADC_DCLKV18Data clock for ADCOutput2.5 V top_HC_ADC_DINU18Data input for ADCOutput2.5 V top_HC_ADC_DOUTL18Data output for ADCInput2.5 V top_HC_ADC_PENIRQ_NN17Pen interrupt ADC (active low)Input2.5 V LCD Panel Interface top_HC_SCENM6Serial clock enableOutput2.5 V top_HC_SDAT2Serial data enableBidirectional2.5 V Video Pipeline Interface top_clk_to_offchip_videoD14Clock for LCD touch panelOutput2.5 V top_HC_DENR17Data enable for ADCOutput2.5 V top_HC_HDM14LCD horizontal sync inputOutput2.5 V top_HC_VDL13LCD vertical sync inputOutput2.5 V top_HC_LCD_DATA0R4Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA1T17Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA2T18Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA3L16Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA4M17Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA5N6Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA6M13Multiplexed RGB data for LCD touch panel Output2.5 V top_HC_LCD_DATA7N13Multiplexed RGB data for LCD touch panel Output2.5 V 10/100 Ethernet Interface (National PHY DP83848C) top_HC_ETH_RESET_NH18Ethernet PHY reset (active low)Output2.5 V top_HC_MDCP18Management data clockOutput2.5 V top_HC_MDION7Management data I/OBidirectional2.5 V top_HC_RX_CLKF17MII receive clockInput2.5 V top_HC_RX_COLG17MII collision detectInput2.5 V top_HC_RX_CRSL3MII carrier sense/receiveInput2.5 V top_HC_RX_D0P2Receive dataInput2.5 V top_HC_RX_D1P1Receive dataInput2.5 V Table 1. Signal Descriptions (Part 4 of 5) Pin Name Location Signal Description Direction I/O Standard DescriptionPage 9 March 2009 Altera CorporationNios II 3C25 Microprocessor with LCD Controller Data Sheet Table 2 lists the device pin-outs. top_HC_RX_D2T3Receive dataInput2.5 V top_HC_RX_D3R3Receive dataInput2.5 V top_HC_RX_DVG18Receive data validInput2.5 V top_HC_RX_ERRL4Receive errorInput2.5 V top_HC_TX_CLKN18MII transmit clockInput2.5 V top_HC_TX_D0M18Transmit dataOutput2.5 V top_HC_TX_D1L14Transmit dataOutput2.5 V top_HC_TX_D2L15Transmit dataOutput2.5 V top_HC_TX_D3P17Transmit dataOutput2.5 V top_HC_TX_ENL17Transmit enableOutput2.5 V SD/MMC Card Interface top_HC_SD_CLKM2SD clockOutput2.5 V top_HC_SD_CMDL6SD commandOutput2.5 V top_HC_SD_DATM3SD dataInput2.5 V top_HC_SD_DAT3N8SD data3Output2.5 V EEPROM (24LC00) Interface top_HC_ID_I2CDATD3Serial dataBidirectional2.5 V top_HC_ID_I2CSCLH6Serial clockOutput2.5 V RS-232 UART Transceiver ADM3202 Interface top_HC_UART_RXDE18UART receive dataInput2.5 V top_HC_UART_TXDH17UART transmit dataOutput2.5 V LED Interface top_led0P13LED outputOutput2.5 V top_led1T1LED outputOutput2.5 V Push Button Interface top_button0F1Parallel I/O for push buttonInput2.5 V top_button1F2Parallel I/O fo