testbanch+Verilog在Modelsim实现3分频及5分频.doc

用Verilog语言写的三分频电路/上升沿触发的分频设计module three(clkin, clkout);input clkin;/定义输入端口output clkout;/定义输出端?reg 1:0 step1, step;always (posedge clkin)begincase (step)2b00: step=2b01;2b01: step=2b10;2b10: step=2b00;default :step=2b00;endcaseendalways (negedge clkin)begincase (step1)2b00: step1=2b01;2b01: step1=2b10;2b10: step1=2b00;default :step1=2b00;endcaseendassign clkout=(step1|step11);endmoduleTestbanch：timescale1ns/100psmodule div3_tb ; wire clkout; reg clkin ; wire 1:0 step1, step; initial begin clkin=0; end always #2 clkin=clkin; div3 DUT ( .clkin (clkin) , .clkout (clkout), .step1(step1), .step(step) ); endmodule 用Verilog语言写五分频电路，占空比为50：module div_5 ( clkin,rst,clkout );input clkin,rst;output clkout;reg 2:0 step1, step2;always (posedge clkin )if(!rst)step1=3b000;else begincase (step1)3b000: step1=3b001;3b001: step1=3b011;3b011: step1=3b100;3b100: step1=3b010;3b010: step1=3b000;default:step1=3b000;endcaseendalways (negedge clkin )if(!rst)step2=3b000;elsebegincase (step2)3b000: step2=3b001;3b001: step2=3b011;3b011: step2=3b100;3b100: step2=3b010;3b010: step2=3b000;default:step2=3b000;endcaseendassign clkout=step10|step20;endmoduleTestbanch：module div5_tb ; reg rst ; reg clkin ; wire clkout ; wire 2:0 step1, step2; initial begin clkin=0; end always #10 clkin=clkin; initial begin rst=0; #20 rst=1; #2000 $finish; end div5 DUT ( .rst (rst ) , .clkin