哈工大深研院数字集成电路2012期末试题.pdf

Page No. 1 哈尔滨工业大学深圳研究生院 2012 年 秋 季学期期末考试试卷 HIT Shenzhen Graduate School Examination Paper Course Name: Theory and design of digital IC Lecturer: Zhang， Yan Question One Two Three Four Five Six Seven Eight Nine Ten Total Mark Question One: Explain the following concepts. (20 points) 1. Clock skew and clock jitter 2. Logic effort and effective fan-out 3. Pipeline design 4. Latch and register Question Two: Please describe the detailed functionalities of the following two circuits . (20 points) Student Name: Student ID: Major: 答题内容写在边线外视为无效 Page No. 2 Question Three: Consider the circuit of the following figure, VDD DC B A Y AB C D (a) what is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices such that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. (10 pointers) (b) What are the input patterns that give the worst case pHL t and pLH t. State clearly what are the initial input patterns and which inputs has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes. (10 points) Question Four: Design a domino circuit whose output is: out AB BC C Assume we have access to true form of the inputs only (A, B and C). Draw a transistor level schematic. (20 pointers) Question Five: (20 points) a) Setup = 150ps, Thold = 0,Tcq = 50ps, and Tlogic = 250ps. Find the maximum clock frequency? b) There is a clock skew for Reg. B relative to Reg. A. Find the maximum possible clock