VHDL驱动四位一体数码管(我们仅仅使用了一组段选,绝无仅有).doc

我们仅仅使用了一组段选（绝无仅有）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity jishi isport( clk: in std_logic; -Info: Assuming node clk is an undefined clock dout: out std_logic_vector(7 downto 0); wout: out std_logic_vector(0 to 3) );end jishi;architecture first of jishi is signal newclk :std_logic; -Info: Detected ripple clock newclk as buffer signal a :integer range 0 to 200 :=0; signal wei :integer range 0 to 2 :=0; signal count1:integer range 0 to 9 :=0; signal count2:integer range 0 to 9 :=0; signal count3:integer range 0 to 7 :=0; signal dout1:std_logic_vector(7 downto 0); signal dout2:std_logic_vector(7 downto 0); signal dout3:std_logic_vector(7 downto 0); begin U1:process(clk) begin if a=200 then a = 0 ; elsif clkevent and clk=1 then if a=99 then newclk=0; -becausenewclkis std_logic type.so we must use1,not 1 else newclk=1; -becauseais integer type.so we must use 1,not 1 end if; a=a+1; end if; end process U1; U2:process(newclk) begin if newclkevent and newclk=1then if count1 = 9 then count1=0; count2=count2+1; else count1=count1+1; end if; if count2 = 9 then count2=0; count3=count3+1; elsif count3=7 then count3=0; end if; end if; end process U2; U3:process(newclk) begin if newclkevent and newclk=1then if wei=2 then wei=0; else weidout1dout1dout1dout1dout1dout1dout1dout1dout1dout1 null; end case; end process U4; U5:process(count2) begin case count2 is -Warning (13410): Pin dout7 is stuck at VCC when 0 =dout2dout2dout2dout2dout2dout2dout2dout2dout2dout2 null; end case; end process U5; U6:process(count3) begin case count3 is -Warning (13410): Pin dout7 is stuck at VCC when 0 =dout3dout3dout3dout3dout3dout3dout3dout3 null; end case; end process U6; U7:process(wei) begin case wei is when 0 = dout=