中科院_段成华_专用集成电路设计_作业5详解.docx

assignment 51. analyze se of actel act (figure 5.4(d) with any possible combinations of c1, c2 and clr c controls. a. which functions does se support? b. verify these functions by using modelsim simulator at logic level or hspice circuit simulator.figure 5.4(d) actel act 2 and act 3 logic modules: the equivalent circuit (without buffering) of the se (sequential element)solution:a）由图中逻辑关系可以得出q=(c1/c2+clr)(/(c1c2) (/s1d+f1s1) mcf1+(c1c2)q)(clr+c1/c2)b)由于在设计中c1和c2至少要有一个接clk(否则设计无意义)则编写相应的hspice仿真代码如下* homeworkfive.sp- actel act. d:program files (x86)synopsyshspice_d-2010.03-sp1mm018.l tt * set tsmc 0.18um library.option list node post.tran 50p 5000p* starts a transient analysis that simulates a circuit at a specific time.* format: .tran tstep1 tstop1 .probe tran+ clock=par(v(c1)+ data=par(v(d)+ q=par(v(q)* use this command to save output variables to interface and graph data* files. the parameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * the node voltages that you specify in the .ic statement are fixed to* determine the dc operating point. they are used only in the first * iteration to set an initial guess for the dc operating point analysis.* waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c1 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vc1 c2 gnd 0* top: d-latch* xclkinv clck clckn inv $ enable if asymmetric (overlapping) positive* and negative clocks are usedxact d c1 c2 clr q act cw1 qm gnd .1f $ add wire delaycw2 q gnd .1f* macro definitions* n-channel mosfet* drain gate source.subckt nmos n1 n2 n3mn n1 n2 n3 gnd nch l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4u .ends nmos* p-channel mosfet* drain gate source .subckt pmos n1 n2 n3vcc vcc gnd 1.8 *vcc definitionmp n1 n2 n3 vcc pch l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmos*.subckt tgate in out c cnxmn in c out nmos *1 signal via nmosxmp in cn out pmos *0 signal via pmos.ends tgate*.subckt inv in outvcc vcc gnd 1.8xmn out in gnd nmosxmp out in vcc pmos.ends inv*.subckt or a b yvcc vcc gnd 1.8xmp1 d1 a vcc pmosxmp2 yn b d1 pmosxmn1 yn a gnd nmosxmn2 yn b gnd nmosxinv yn y inv.ends or*.subckt and a b yvcc vcc gnd 1.8xmp1 yn a vcc pmos xmp2 yn b vcc pmosxmn1 yn a s1 nmosxmn2 s1 b gnd nmosxinv yn y inv.ends and*.subckt xnor a b yvcc vcc gnd 1.8xand a b y1 andxor1 a b y2 orxinv y2 y2n invxor2 y1 y2n y or.ends xnor*.subckt mux a b s zxinv s sn invxtg1 a z s sn tgatextg2 b z sn s tgate.ends mux*.subckt act d c2 c1 clr qxinv1 c1 c1n invxinv2 c2 c2n invxg1 c2 c1n s1 andxg2 c2n c1 t andxg3 c2 c1 s2 xnorxg4 t clr mc orxg5 qm d s1 m muxxg6 m mc qm andxg7 q qm s2 s muxxg8 s mc q and.ends act*.end 如代码所示，假设c1接clk而c2接地时，此时act芯片被配置成一个d触发器它在下降沿将d信号送入触发器，并且具有下降沿清零的功能。 c2接clk而c1接地时，此时act芯片被配置成一个d触发器它在上升沿将d信号送入触发器，并且具有下降沿清零的功能。代码更改如下 clock=par(v(c2)+ data=par(v(d)+ q=par(v(q)* use this command to save output variables to interface and graph data* files. the parameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * the node voltages that you specify in the .ic statement are fixed to* determine the dc operating point. they are used only in the first * iteration to set an initial guess for the dc operating point analysis.* waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c2 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vc1 c1 gnd 0 c2接1而c1接clk时，此时act芯片被配置成一个d触发器它在上升沿将d信号送入触发器，并且具有异步清零的功能。代码更改如下 + clock=par(v(c1)+ data=par(v(d)+ q=par(v(q)* use this command to save output variables to interface and graph data* files. the parameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * the node voltages that you specify in the .ic statement are fixed to* determine the dc operating point. they are used only in the first * iteration to set an initial guess for the dc operating point analysis.* waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c1 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vc1 c2 gnd 1.8很明显在第一个d信号处出现了亚稳定状态，判决出现了失误。c2接clk而c1接1，clr接1时，此时act芯片被配置成一个在低电平作用下的透明锁存器。代码更改如下+ clock=par(v(c2)+ data=par(v(d)+ q=par(v(q)* use this command to save output variables to interface and graph data* files. the parameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * the node voltages that you specify in the .ic statement are fixed to* determine the dc operating point. they are used only in the first * iteration to set an initial guess for the dc operating point analysis.* waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c2 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)*vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vclr clr gnd 1.8vc1 c1 gnd 1.8c1接clk而c2接0，clr接1时，此时act芯片被配置成一个在高电平作用下的透明锁存器。代码更改如下+ clock=par(v(c1)+ data=par(v(d)+ q=par(v(q)* use this command to save output variables to interface and graph data* files. the parameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * the node voltages that you specify in the .ic statement are fixed to* determine the dc operating point. they are used only in the first * iteration to set an initial guess for the dc operating point analysis.* waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c1 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)*vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vclr clr gnd 1.8vc2 c2 gnd 02. splitting the xc3000 clb smith_asicsin section 5.2.1 we noted “you can split the (xc3000) 32-bit lut in half, using one of the seven input variables to switch between the f and g outputs. this technique can implement some functions of six and seven variables.”a. show which functions of six and seven variables can, andfgb. which functions cannot, be implemented using this method.solution:可实现的函数例子f6_var_some=ef(a,b,c,d)+/eg(a,b,qx,d)f6_var_some=/ef(a,qx,c,d)+eg(a,b,qx,d)通过观察可以发现可以实现的6变量函数具有如下特点1）a、d、e必须存在2）f和g中函数的变量仅有一个不同3)一旦f和g中额外引入的变量确定则剩余一个填充变量也随之确定因此可以推测能实现的六变量函数变量变