EDA电子钟的设计.doc

电子设计自动化EDA课程设计 题目 电 子 钟 设 计 专业 电子信息科学与技术 班级 * 学号 * 姓名 * 18目录一、设计目的和要求21.1设计目的21.2设计要求2二、模块划分2三、功能简介2四、各模块源代码31.分频模块52.闹钟模块53.跑表模块63.1毫秒代码63.2秒代码73.3分代码73.4跑表顶层代码84.扫描模块95.选择模块115.1三选一代码115.2键选择模块126.时钟模块136.1分秒代码136.2小时代码136.3时钟顶层代码147. 顶层代码15五、RTL viewer.17六、引脚锁定和下载测试181.引脚锁定182.下载测试18七、不足及改进18八、心得体会.19参考文献20一、设计目的和要求1.1设计目的 1、更加熟练掌握本学科知识，更加了解VHDL的设计。 2、进一步掌握电子电路的一般设计方法。 3、掌握层次化设计、元件例化和顶层设计概念，了解模块之间的连接。 4、培养提出问题，独立分析问题，认真解决问题的能力。1.2设计要求设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。 扩展功能要求：跑表功能，闹钟功能，调整数码管的亮度。 选择GW48-EDA系统的电路模式7;数码管8左边的跳线选择CLOSE。二、模块划分分频模块、时钟模块、闹钟模块、跑表模块、显示模块、选择模块三、功能简介 1、本电子钟使用分频器将10MHZ分成1HZ、100HZ、5000HZ分别用来用于时钟正常走时，跑表正常跑表和扫描电路扫描数码管。2、 时钟模块：分为时、分、秒三个模块，时采用24进制，分秒采用60进制。1HZ驱动秒正常走时，当59秒时，秒显示变为0，同时产生进位，驱动分开始计时，当59分时，分显示变为0，同时产生进位，驱动时开始计时，当23:59:59时，时钟复位。并通过键可调节时间。3、 跑表模块：分为分、秒、毫秒三个模块，使用100HZ频率驱动毫秒开始计时，当99ms时，毫秒清零，产生进位驱动秒开始计时，以此类推。4、 闹钟模块：用户可通过键设置闹钟时间，当时钟到达闹钟时间，扬声器响起，时间为一分钟，用户也可以通过键自行关闭。5、 显示模块：采用5000HZ的频率驱动扫描电路，通过扫描电路，将时钟输出显示在数码管上。同时可以调节数码管亮度。6、 按键说明：键7是用来选择三个显示模式，初始时选择为电子表，按一下显示闹钟，再按一下显示跑表；键8、键5和键4是用在表或闹钟的模式下调节电子表和闹钟的小时和分钟；键1用于选择电路的时钟信号，用来控制调时时的单一性变动；键8和键5在跑表的模式下则用作复位键与暂停键；键4在跑表的模式下可用于调节亮度。四、各功能源代码1.分频模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FENPIN ISPORT(CLK:IN STD_LOGIC;-时钟信号，10MHZ CLK1H:OUT STD_LOGIC;-1HZ输出 CLK100H:OUT STD_LOGIC;-100HZ输出 CLK5000H:OUT STD_LOGIC);-5000HZ输出END;ARCHITECTURE ONE OF FENPIN ISSIGNAL TEMP1,TEMP2,TEMP3:STD_LOGIC;SIGNAL COUT_1:INTEGER RANGE 0 TO 4999999;SIGNAL COUT_2:INTEGER RANGE 0 TO 49999;SIGNAL COUT_3:INTEGER RANGE 0 TO 999;BEGINREX1:PROCESS(CLK) -1HZ分频 BEGIN IF CLKEVENT AND CLK=1 THEN IF COUT_14999999 THEN COUT_1=COUT_1+1; ELSECOUT_1=0; TEMP1=NOT TEMP1; END IF; END IF; END PROCESS REX1;REX2:PROCESS(CLK) -100HZ分频 BEGIN IF CLKEVENT AND CLK=1 THEN IF COUT_249999 THEN COUT_2=COUT_2+1;ELSECOUT_2=0; TEMP2=NOT TEMP2; END IF; END IF; END PROCESS REX2;REX3:PROCESS(CLK) -5000HZ分频 BEGIN IF CLKEVENT AND CLK=1 THEN IF COUT_3999 THEN COUT_3=COUT_3+1;ELSECOUT_3=0; TEMP3=NOT TEMP3; END IF; END IF; END PROCESS REX3; CLK1H=TEMP1;CLK100H=TEMP2;CLK5000H=TEMP3;END ONE;2.闹钟模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY NAOZHONG IS PORT(CLK,S_SE,F_SE,conK : IN STD_LOGIC;- 闹钟分、时选择、调节 BH_OUT1, BM_OUT1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-闹钟的分、时输入 NZS_OUT, NZF_OUT :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); SPEAKER_OUT:OUT STD_LOGIC);-扬声器END ENTITY;ARCHITECTURE ONE OF NAOZHONG ISSIGNAL CL: INTEGER RANGE 0 TO 6000;SIGNAL SS,FS:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN ONE:PROCESS(S_SE,F_SE,conK) BEGIN IF S_SE=1 THEN -闹钟调时 IF conKEVENT AND conK=1 THEN IF SS(3 DOWNTO 0)1001 THEN SS(3 DOWNTO 0)=SS(3 DOWNTO 0)+1; ELSE SS(3 DOWNTO 0)=0000;SS(7 DOWNTO 4)=SS(7 DOWNTO 4)+1; END IF; IF SS(7 DOWNTO 4)=0010 AND SS(3 DOWNTO 0)=0011 THEN SS(7 DOWNTO 4)=0000;SS(3 DOWNTO 0)=0000; END IF; END IF; END IF; IF F_SE=1 THEN -闹钟调分 IF conKEVENT AND conK=1 THEN IF FS(3 DOWNTO 0)1001 THEN FS(3 DOWNTO 0)=FS(3 DOWNTO 0)+1; ELSE FS(3 DOWNTO 0)=0000;FS(7 DOWNTO 4)=FS(7 DOWNTO 4)+1; END IF; IF FS(7 DOWNTO 4)=0101 AND FS(3 DOWNTO 0)=1001 THEN FS(7 DOWNTO 4)=0000;FS(3 DOWNTO 0)=0000; END IF; END IF; END IF; END PROCESS ONE; NZS_OUT=SS;NZF_OUT=FS;COM:PROCESS(BH_OUT1, BM_OUT1, NZS_OUT, NZF_OUT) BEGIN IF BH_OUT1=NZS_OUT AND BM_OUT1=NZF_OUT THEN SPEAKER_OUT=CLK; END IF; END PROCESS COM;REG:PROCESS(CLK) -扬声器频率定义 BEGIN IF CLKEVENT AND CLK=1 THEN IF CL6000 THEN CL=CL+1; ELSE CL=0; END IF; END IF; END PROCESS REG;END ONE;3.跑表模块3.1毫秒代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY haomiao IS PORT(CLK,RST,EN:IN STD_LOGIC; -时钟信号、复位和使能 HB_CO:OUT STD_LOGIC;-进位端 HB_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HB_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -高低位输出END ENTITY;ARcHITECTURE ONE OF haomiao ISSIGNAL PS,PG:STD_LOGIC_VECTOR(3 DOWNTO 0);-高低位信号SIGNAL CO:STD_LOGIC;-进位信号BEGINPROCESS(CLK,RST)BEGINIF RST=1 THEN PS=0000;PG=0000; ELSIF CLKEVENT AND CLK=1 THEN IF EN=1 THEN IF PG1001 THEN PG=PG+1; ELSE PG=0000; PS=PS+1;CO=0; IF PS=1001 AND PG=1001 THEN PS=0000;PG=0000;CO=1; END IF; END IF; END IF;END IF;END PROCESS; HB_OUTS=PS;HB_OUTG=PG;HB_CO=CO;END ONE;3.2秒代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY miao IS PORT(CLK,RST,EN:IN STD_LOGIC; M_CO:OUT STD_LOGIC; M_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY;ARcHITECTURE ONE OF miao ISSIGNAL PS,PG:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL CO:STD_LOGIC;BEGINPROCESS(CLK)BEGINIF RST=1 THEN PG=0000;PS=0000;ELSIF CLKEVENT AND CLK=1 THEN IF PG1001 THEN PG=PG+1; ELSE PG=0000; PS=PS+1;CO=0; IF PS=0101 AND PG=1001 THEN PS=0000;PG=0000;CO=1; END IF; END IF;END IF;END PROCESS; M_OUTS=PS;M_OUTG=PG;M_CO=CO;END ONE;3.3分代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY fen IS PORT(CLK,RST,EN:IN STD_LOGIC; F_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); F_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY;ARcHITECTURE ONE OF fen ISSIGNAL PS,PG:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL CO:STD_LOGIC;BEGINPROCESS(CLK)BEGINIF RST=1 THEN PG=0000;PS=0000;ELSIF CLKEVENT AND CLK=1 THEN IF PG1001 THEN PG=PG+1; ELSE PG=0000; PS=PS+1; IF PS=0101 AND PG=1001 THEN PS=0000;PG=0000; END IF; END IF;END IF;END PROCESS; F_OUTS=PS;F_OUTGCLKP,EN=ENP,RST=RSTP,HB_CO=HMS,HB_OUTS=PBH_OUT(7 DOWNTO 4),HB_OUTG=PBH_OUT(3 DOWNTO 0);U2:MIAO PORT MAP(CLK=HMS,EN=ENP,RST=RSTP,M_CO=MFS,M_OUTS=PBM_OUT(7 DOWNTO 4),M_OUTG=PBM_OUT(3 DOWNTO 0);U3:FEN PORT MAP(CLK=MFS,EN=ENP,RST=RSTP,F_OUTS=PNM_OUT(7 DOWNTO 4),F_OUTG=PNM_OUT(3 DOWNTO 0);END ONE;4.扫描模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY saomiao IS PORT( CLK,LD_SET,LD_K:IN STD_LOGIC; SMS,SMF,SMM:IN STD_LOGIC_VECTOR(7 downto 0); DK: OUT STD_LOGIC_VECTOR(6 downto 0); -段控制信号； WK: OUT STD_LOGIC_VECTOR(7 downto 0);-位控制信号；END ENTITY;ARCHITECTURE ONE OF saomiao IS SIGNAL SM:STD_LOGIC_VECTOR(2 DOWNTO 0); -扫描信号；SIGNAL A: STD_LOGIC_VECTOR(3 DOWNTO 0);-外部输入信号SIGNAL LIGHT:STD_LOGIC;SIGNAL COUNT:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL COUNT_CLK1,COUNT_CLK2,COUNT_CLK3:INTEGER RANGE 0 TO 6;SIGNAL LD_SETS:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINMP1:PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN IF SM111 THEN SM=SM+1; ELSE SM WK=00000001;A_IN WK=000000&LIGHT&0;A_IN WK=00000&LIGHT&00;A_IN WK=0000&LIGHT&000;A_IN WK=000&LIGHT&0000;A_IN WK=00&LIGHT&00000;A_IN WK=0&LIGHT&000000;A_IN WK=LIGHT&0000000;A_IN DK DK DK DK DK DK DK DK NULL; END CASE; END PROCESS MP3;MP4:PROCESS(LD_SETS,LD_K) BEGIN IF LD_SETS =10 THEN IF LD_KEVENT AND LD_K=1 THEN COUNT LIGHT IF COUNT_CLK1=2 THEN LIGHT=1 ;COUNT_CLK1=0;ELSE LIGHT=0 ;COUNT_CLK1 IF COUNT_CLK2=4 THEN LIGHT=1 ;COUNT_CLK2=0;ELSE LIGHT=0 ;COUNT_CLK2 IF COUNT_CLK3=6 THEN LIGHT=1 ;COUNT_CLK3=0;ELSE LIGHT=0 ;COUNT_CLK3=COUNT_CLK3+1;END IF;END CASE;END IF;END PROCESS MP5;MP6:PROCESS(LD_SET)BEGIN IF LD_SETEVENT AND LD_SET=1 THEN IF LD_SETS2 THEN LD_SETS=LD_SETS+1; ELSE LD_SETS=00; END IF;END IF ;END PROCESS MP6;END ONE; 5.选择模块5.1三选一代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MUX31A IS PORT(CLK:IN STD_LOGIC;-时钟信号，接选择键键7 DH,DM,DS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-电子表时、分、秒输入 NH,NM:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-闹钟时、分输入 PF,PM,PH:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-跑表分、秒、毫秒输入 P1,P2,P3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-选择输出END ENTITY;ARCHITECTURE ONE OF MUX31A IS SIGNAL X1,X2,X3:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL Q: INTEGER RANGE 0 TO 2;-内部选择信号BEGIN PROCESS(CLK)BEGINIF CLKEVENT AND CLK=1 THEN IF Q2 THEN Q=Q+1;ELSE QX1=DH;X2=DM;X3X1=NH;X2=NM;X3X1=PF;X2=PM;X3=PH;END CASE;END PROCESS;P1=X1;P2=X2;P3=X3;END ONE;5.2键选择模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XUANZE IS PORT(CLK:IN STD_LOGIC;-时钟信号，接键1 ANJIAN8,ANJIAN5:IN STD_LOGIC; NH_SET,NM_SET:OUT STD_LOGIC;-电子表时分设置 NS_SET,NF_SET:OUT STD_LOGIC);-闹钟时分设置END ENTITY;ARCHITECTURE ONE OF XUANZE ISSIGNAL S :INTEGER RANGE 0 TO 2;SIGNAL NH,NM:STD_LOGIC;-电子表时分设置信号SIGNAL NS,NF:STD_LOGIC;-闹钟时分设置信号BEGIN p1:PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN IF S1 THEN S=S+1; ELSE S NH=ANJIAN8;NM=ANJIAN5;NS=0;NF NS=ANJIAN8;NF=ANJIAN5;NH=0;NM NH=0;NM=0;NS=0;NF NULL; END CASE; end process p2;NH_SET=NH;NM_SET=NM;NS_SET=NS;NF_SET=NF;END ONE;6.时钟模块6.1分秒代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MS60V IS PORT(CLK:IN STD_LOGIC; MS_CO:OUT STD_LOGIC; MS_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); MS_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY;ARCHITECTURE ONE OF MS60V ISSIGNAL PS,PG:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL CO:STD_LOGIC; -内部高低位进位信号BEGIN PROCESS(CLK)BEGIN IF CLKEVENT AND CLK=1 THEN IF PG1001 THEN PG=PG+1; CO=0; -低位小于9时，自动加1，不进位 ELSE PG=0000; PS=PS+1;CO=1;CO=0;-大于9时，自动清零，进位，高位加1 IF PS=0101 AND PG=1001 THEN PS=0000;PG=0000;CO=1; END IF; -当为59时，自动清零，并产生进位 END IF; END IF; END PROCESS; MS_OUTS=PS;MS_OUTG=PG;MS_CO=CO;END ONE;秒时钟CLK为1HZ，分时钟CLK接秒进位端，Ms_Outs为分秒高位输出，Ms_Outg为分秒低位输出，MS_CO为分秒的进位。6.2小时代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY HOUR_24V IS PORT(CLK:IN STD_LOGIC; -CLK接分钟进位端 HOUR_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-高位输出 HOUR_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -低位输出END ENTITY;ARCHITECTURE SECOND OF HOUR_24V ISSIGNAL PS,PG:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN IF PG1001 THEN PG=PG+1; -低位小于9时，自动加1 ELSE PG=0000;PS=PS+1; -大于9时，高位自动加1 END IF; IF PS=0010 AND PG=0011 THEN PS=0000;PG=0000; END IF; -当23时，自动清零 END IF; END PROCESS; HOUR_OUTS=PS; HOUR_OUTG=PG;END SECOND;6.3时钟顶层代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY dianzibiao IS PORT(CLKQ:IN STD_LOGIC; -时钟信号； bh_SET, NM_SET:IN STD_LOGIC;-钟的小时与分钟设置； B_K:IN STD_LOGIC; -钟的小时与分钟调节 BH_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-小时输出； BM_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-分钟输出； NH_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-秒表输出：END ENTITY;ARCHITECTURE ONE OF dianzibiao ISCOMPONENT MS60V -分秒声明； PORT(CLK:IN STD_LOGIC; MS_CO:OUT STD_LOGIC; MS_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); MS_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT;COMPONENT HOUR_24V -小时声明；PORT(CLK:IN STD_LOGIC; HOUR_OUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HOUR_OUTG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT;SIGNAL SML,MHL:STD_LOGIC; -进位端连接信号SIGNAL MIN_1,MIN_2,MIN: STD_LOGIC; SIGNAL SMIN_1,SMIN_2,SMIN: STD_LOGIC;BEGIN* *SMIN_1=MHL AND (NOT bh_SET);SMIN_2=bh_SET AND B_K;SMINCLKQ,MS_CO=SML,MS_OUTS(3 DOWNTO 0)=NH_OUT(7 DOWNTO 4),MS_OUTG(3 DOWNTO 0)=NH_OUT(3 DOWNTO 0);U2:MS60V PORT MAP(CLK=MIN,MS_CO=MHL,MS_OUTS(3 DOWNTO 0)=BM_OUT(7 DOWNTO 4),MS_OUTG(3 DOWNTO 0)=BM_OUT(3 DOWNTO 0);U3:HOUR_24V PORT MAP(CLK=SMIN,HOUR_OUTS(3 DOWNTO 0)=BH_OUT(7 DOWNTO 4),HOUR_OUTG(3 DOWNTO 0)=BH_OUT(3 DOWNTO 0);END ONE;7.顶层代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DIANZIZHONG IS PORT(CLKZ,JIAN4,JIAN5,JIAN7,JIAN8,JIAN1:IN STD_LOGIC;-时钟信号和控制键 CLOCK_DK: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-段控制信号； CLOCK_WK: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-位控制信号； SPEAKER:OUT STD_LOGIC);END ENTITY;ARCHITECTURE ONE OF DIANZIZHONG ISCOMPONENT FENPIN IS -分频声明PORT(CLK:IN STD_LOGIC; CLK1H:OUT STD_LOGIC; CLK100H:OUT STD_LOGIC; CLK5000H:OUT STD_LOGIC);END COMPONENT;COMPONENT DIANZIBIAO -走时声明 PORT(CLKQ:IN STD_LOGIC;-走时的时钟信号； BH_SET, NM_SET:IN STD_LOGIC;-走时的小时与分钟设置； B_K:IN STD_LOGIC; -走时的小时与分钟调节； BH_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-走时的小时输出； BM_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-走时的分钟输出； NH_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-走时的秒表输出：END COMPONENT;COMPONENT PAOBIAO -跑表声明 PORT(CLKP,ENP,RSTP:IN STD_LOGIC; PNM_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-跑表分控制 PBM_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-跑表秒控制 PBH_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-跑表毫秒控制END COMPONENT;COMPONENT NAOZHONG -闹钟声明PORT(CLK,S_SE,F_SE,con : IN STD_LOGIC; BH_OUT1, BM_OUT1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); NZS_OUT, NZF_OUT :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); SPEAKER_OUT:OUT STD_LOGIC);END COMPONENT;COMPONENT XUANZE IS -键选择声明PORT(CLK:IN STD_LOGIC; ANJIAN8,ANJIAN5:IN STD_LOGIC; NH_SET,NM_SET:OUT STD_LOGIC; NS_SET,NF_SET:OUT STD_LOGIC);END COMPONENT;COMPONENT SAOMIAO -扫描声明 PORT( CLK,LD_SET,LD_K:IN STD_LOGIC; SMS,SMF,SMM:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DK: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -段控制信号； WK: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-位控制信号；END COMPONENT;COMPONENT MUX31A -三选一选择器声明；PORT(CLK:IN STD_LOGIC; DH,DM,DS:IN STD_LOGIC_VECTOR(7 DOWNTO 0); NH,NM:IN STD_LOGIC_VECTOR(7 DOWNTO 0); PF,PM,PH:IN STD_LOGIC_VECTOR(7 DOWNTO 0); P1,P2,P3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT;SIGNAL B_CLK,PB_CLK,SM_CLK:STD_LOGIC;-分频模块与其他模块的CLK连接信号SIGNAL XZ_NH,XZ_NM,XZ_NS,XZ_NF:STD_LOGIC;-选择与走时模块连接信号SIGNAL DH_IN,DM_IN,DS_IN: STD_LOGIC_VECTOR(7 DOWNTO 0);-与走时模块连接信号SI