关于单片机AT89C51的部分英文资料及翻译.doc

南 京 工 程 学 院毕业设计文献资料翻译 （原文及译文） 原文名称 ：the general situation of at89c51 课题名称： 电子密码锁的设计与实现 学生姓名： 姜子浩 学 号： 240102518 指导老师： 朱 瑾 所在院系： 康尼学院 专业名称： 电 子 信 息 工 程 2014 年 2 月 南 京the general situation of at89c51micro controllers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. the high processing speed and enhanced peripheral set of these micro controllers make them suitable for such high-speed event-based applications.however, these critical application domains also require that these micro controllers are highly reliable. the high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these micro controllers both at the component and at the system level. intel platform engineering department developed an object-oriented multi threaded test environment for the validation of its at89c51 automotive micro controllers. the goals of this environment was not only to provide a robust testing environment for the at89c51 automotive micro controllers, but to develop an environment which can be easily extended and reused for the validation of several other future micro controllers. the environment was developed in conjunction with microsoft foundation classes (at89c51). the paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use at89c51.1.1 introductionthe 8-bit at89c51 chmos micro controllers are designed to handle high-speed calculations and fast input/output operations. mcs 51 micro controllers are typically used for high-speed event control systems. commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. the automotive industry use mcs 51 micro controllers in engine-control systems, airbags, suspension systems, and antilock braking systems (abs). the at89c51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a cpu with above average processing power in a single package. the financial and legal risk of having devices that operate unpredictably is very high. once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. redesign costs can run as high as a $500k, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. in addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. to mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.this complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.intel chandler platform engineering group provides post silicon system validation (sv) of various micro-controllers and processors. the system validation process can be broken into three major parts.the type of the device and its application requirements determine which types of testing are performed on the device.1.2 the at89c51 provides the following standard features: 4kbytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bit timer/counters, a five vector two-level interrupt architecture,a full duple serial port, on-chip oscillator and clock circuitry.in addition, the at89c51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters,serial port and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1.3 pin descriptionvcc：supply voltage.gnd：ground.port 0：port 0 is an 8-bit open-drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high impedance inputs.port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. in this mode p0 has internal pull ups.port 0 also receives the code bytes during flash programming,and outputs the code bytes during program verification. external pull ups are required during program verification.port 1：port 1 is an 8-bit bi-directional i/o port with internal pullups.the port 1 output buffers can sink/source four ttl inputs.when 1s are written to port 1 pins they are pulled high by the internal pull ups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil) because of the internal pull ups.port 1 also receives the low-order address bytes during flash programming and verification.port 2：port 2 is an 8-bit bi-directional i/o port with internal pull ups.the port 2 output buffers can sink/source four ttl inputs.when 1s are written to port 2 pins they are pulled high by the internal pull ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil) because of the internal pull ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to port 2 pins that are externally being pulled low will source current (iil) because of the internal pull ups.port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movxdptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register.port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3：port 3 is an 8-bit bi-directional i/o port with internal pull ups.the port 3 output buffers can sink/source four ttl inputs.when 1s are written to port 3 pins they are pulled high by the internal pull ups and can be used as inputs. as inputs,port 3 pins that are externally being pulled low will source current (iil) because of the pull ups.port 3 also serves the functions of various special features of the at89c51 as listed below:rst：reset input. a high on this pin for two machine cycles while the oscillator is running resets the device.ale/prog：address latch enable output pulse for latching the low byte of the address during accesses to external memory.this pin is also the program pulse input (prog) during flash programming.in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory.if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the micro controller is in external execution mode.from：/link?url=q4yhez2_4vssat89c51简介现在的微控制器通常存在于大量的商业应用,如调制解调器、马达-电机控制系统,空调控制系统,汽车引擎和等等。 高处理速度和增强的外围设置这些微控制器使他们适合高速基于事件的应用程序。然而,这些关键应用领域也要求这些微控制器是高度可靠。高可靠性和低市场风险可以确保一个健壮的测试过程和适当的工具环境验证这些微控制器的组件和系统级。英特尔休息平台工程部门开发了一个面向对象的多线程测试环境验证的汽车微控制器at89c51单片机。这种环境下的目标不仅是提供一个健壮的汽车微控制器at89c51单片机的测试环境,但是开发一个有利的环境,可以很容易地扩展和重用的验证其他几个未来的微控制器。开发环境与微软基础类(at89c51)。本文描述了这个测试环境的设计和机制,与各种硬件/软件环境组件的交互,以及如何使用at89c51单片机。1.1 介绍8位微控制器at89c51 chmos旨在处理高速计算和快速的输入/输出操作。mcs 51微控制器控制系统通常用于高速事件。商业应用包括调制解调器、马达-电机系统、打印机、复印机、空调控制系统、磁盘驱动器和医疗器械。汽车行业在研发使用mcs 51微控制器系统,安全气囊、悬架系统、防抱死制动系统(abs)。at89c51尤其适合应用程序受益于它的处理速度和提高片上外围函数集,如汽车传动系的控制,车辆动态悬架,防抱死制动,和稳定控制的应用程序。由于这些关键应用,市场需要一种可靠有效的控制器具有较低的中断延迟响应,服务能力的大量时间和事件驱动整合周边需要实时应用程序,和一个cpu处理能力高于平均水平在一个包中。设备操作的金融和法律风险不可预知的非常高。一旦在市场上,特别是在关键任务应用程序(如一个自动驾驶仪或防抱死制动系统,错误是经济上的。设计成本可以高达500美元,如果修复意味着多2注释它在产品族,共享相同的核心和/或周边设计缺陷。此外,现场更换组件是非常昂贵的,因为设备通常是密封在模块组件的总价值几次。为了减轻这些问题,至关重要的是,控制器进行全面的测试在最坏情况下的组件级和系统级环境和电压条件。这不仅全面、彻底的验证需要一个定义良好的过程也是一个合适的环境和工具来促进和执行任务的成功。英特尔钱德勒平台工程集团提供后硅系统各种微控制器和处理器的验证(sv)。系统验证过程可以分为三个主要部分。设备的类型及其应用需求确定哪些类型的测试都在设备上执行。1.2 at89c51提供了以下功能:4k字节的flash,128字节的内存,32个i/o口,两个16位定时器/计数器、一五级的中断向量,一个完整的二倍的串口,芯片上的振荡器和时钟电路。此外,at89c51设计静态逻辑操作降到零频率和支持两种软件选择节电模式。空闲模式停止cpu同时允许ram、定时器/计数器、串口和中断系统继续运作。这个power-down模式节省ram内容但冻结该振荡器,取消其他芯片功能直至下一次中断或硬件重启。1.3 引脚描述vcc：电压供应。gnd：接地。p0:p0口是一个8位双向i / o端口。作为一个输出端口,每个销可以沉八ttl输入。对端口写着“1”可作为高阻抗输入端用。端口0也可以配置多路复用的