基于单片机的IC卡读写系统开题报告.doc

毕业设计（论文）材料之二（2）本科毕业设计(论文)开题报告题目： 基于单片机的IC卡 读写系统课 题 类 型： 设计 实验研究 论文 学 生 姓 名： 学 号： 专 业 班 级： 学 院： 电气工程学院 指 导 教 师： 开 题 时 间： 2013 年 3月 1 日开题报告内容与要求1、 毕业设计（论文）内容及研究意义（价值）本选题的目的是利用AT89S51单片机微处理器，外接IC卡、键盘模块和显示模块构成一个IC卡读写系统。在理解单片机应用原理的前提下，来提高IC卡读写器的可靠性。在IC卡读写中出现问题时，能及时告警并恢复到正常状态。理解IC的读写软件结构，用具体的软件系统来完成IC卡的读和写的功能。 对于AT89S51单片机它的体积小、质量轻、价格便宜、为学习、应用和开发提供了便利条件。单片机是靠程序的，并且可以修改。通过不同的程序实现不同的功能，尤其是特殊的独特的一些功能。所以，深入掌握单片机的功能可以有效的用单片机来实现IC卡的读与写。 由于IC卡的优点存在于它有超大容量数据存储和非常强大的安全能力，这样就更加的得到人们的由衷的信任和依赖。现在，IC在金融系统和非金融系统等方面都得到很好的应用。如我们的银行卡，电话卡，驾驶员的执照卡,停车收费卡，公交卡，医疗卡等等。IC卡是一个蓬勃发展的行业，一个与我们生活越走越近的产业。在普及因特网和计算机的时候，IC卡扮演着越来越重要的角色。同时IC卡读写器又是IC卡与各个应用系统之间的传输枢纽。因此，基于单片机IC卡读写器设计的研究是一个非常有意义的课题。二、毕业设计（论文）研究现状和发展趋势（文献综述）国内外IC卡市场经过十几年的发展，目前进入到发展的调整阶段中，虽然尚存在着一些问题，但总体发展趋势已经在朝着良好的局面前进。展望未来几年IC卡市场状况，前景将更加美好。具体将体现在以下几个方面： 1）在移动电话领域：移动电话卡仍将是市场的主流产品之一。从出货量来看，未来五年至少将会有20亿张的数量，而发到最终用户手中的卡片也将呈增长的趋势。特别是随着3G时代的来临，将会有大量的增长。 2）在第二代居民身份证换发领域：按照公安部的统一部署，至2008年底，将基本换发完毕，即换发9亿张。第二代居民身份证除公安应用领域外，其应用领域涉及上百余种，如银行、旅馆、股票、邮政、机场、社会保障、工作就业等等。 3）在银行与金融服务业：尽管EMV迁移的动力不足，但其前景还是相当广阔的。目前我国银行磁卡已发卡9亿多张，同时随着我国国力的进一步增强，人民生活水平的不断提高，出国旅游人数剧增，虽然EMV迁移的风险转移越来越突出，但符合EMV2000标准的发卡数量在5年内仍旧会有突破性地增长，到2010年其数量将以千万计。 4）在教育系统学生证件卡及校园一卡通方面：目前教育部和各级地方政府正在探讨教育系统学生证件卡及校园一卡通的统一标准问题。如果一旦实现统一标准，将进一步推动教育事业的发展，其发卡量将数以亿计。 5）在城市交通卡方面：城市交通卡将向区域性一卡通方向发展，如从长三角地区、珠江三角洲向周边地区延伸。 6）在劳动与社会保障卡方面：随着我国社会保障体系的不断完善，加之劳动与社会保障卡已有行业标准，其在五年内发卡量将有明显增长。如上海的社保卡已向乡镇及流动人口发展。 7）在政府机构和企业身份识别和存取管理卡方面：这种卡是解决在共享信息和信息化基础设施的同时，保证系统和信息安全的重要措施。它是基于PKI技术，解决信息的真实性、完整性和不可否认性的要求，保证系统和信息安全，以求不同身份的用户共享信息，各取所需。这种卡的需求量将与日俱增。当然这种卡的形式可以是智能卡的形式，也可以是USB KEY的形式。 8）IC卡向射频识别(RFID)领域发展：国家金卡办自2004年第七届全国IC卡应用工作会后，已把RFID技术和电子标签应用正式列入国家金卡工程重点工作，并着手组织应用试点。经过一年多的调研和探讨，经有关行业和地方申报，已在有条件的部门和地方启动了试点工作，正积极、稳妥地推进RFID应用示范工程建设。如面向工业生产过程与安全生产管理，促进生产力发展；服务于“三农”，推进农业（农产品）产业化；重要物品的防伪和动态管理；供应链与现代物流管理；数字旅游产业与现代服务业等。 IC卡的应用将会越来越广泛。它给人们的工作和生活带来了极大的方便,相信在不远的将来, IC卡会真正走进我们的工作和生活中。在使用IC卡进行信息交流的过程中离不开IC卡读写系统,IC卡读写器就是能将数据信息“写入”IC卡或将IC卡内部的数据信息“读入”或“擦除”的电子接口设备。IC卡读写器的性能和可靠性直接影响读写的能力、准确性和安全性。3、 毕业设计（论文）研究方案及工作计划（含工作重点与难点及拟采用的途径） 对于如何开展本课题的设计，笔者会事先与指导老师进行沟通交流。在了解了课题内容和要求以后，接下来笔者会通过各种途径收集关于本课题的资料。通过相关资料的整理和总结，完成本次毕业设计。对于本次的毕业设计，主程序和各子程序的设计将会是一个难点，学习单片机汇编语言的和主要命令的应用成为眼下重点，为接下来的整体设计做好充分准备。 毕业设计计划进程如下： 3.04-3.10 了解课题，熟悉课题背景3.11-3.17 收集相关资料3.18-3.24 写出并提交开题报告3.25-3.31 研究设计方案4.01-4.07 设计方案细化改进4.08-4.14 硬件系统的设计4.15-4.21 硬件系统的完善4.22-4.28 软件系统的设计4.29-5.05 软件系统的完善5.06-5.12 写出设计论文初稿5.13-5.19 设计论文的修正5.20-5.26 设计论文的修正5.27-6.02 设计报告书修订、完善毕业设计（电子稿）6.03-6.09 提交正式设计报告书（打印版），参加论文互评6.10-6.16 提交正式设计报告书（打印版），参加毕业答辩6.16-6.22 设计报告书答辩后修订，完成毕业设计 四、主要参考文献（不少于10篇，期刊类文献不少于7篇，应有一定数量的外文文献，至少附一篇引用的外文文献（3个页面以上）及其译文）1胡汉才.单片机原理及其接口技术M .北京：清华大学出版社，20042余永权.ATMEL89系列单片机应用技术M.北京：北京航空航天大学出版社，20023李海华 ,王豪才. 用于非接触式IC卡的高频接口模块设计J单片机与嵌入式系统应用，2004(3).4 彭同明，徐学勤单片机原理及应用M北京：中国电力出版社，2005 5 杨秀萍.刘嵩岩. HWZ-201型逻辑加密IC卡读卡器的实现J黑龙江大学自然科学学报2001,18(2).6 苏明强.刘伟.邝涛.高性价比的MIFARE卡读写模块的设计J微计算机信息2006,22(14).7欧伟明. 液晶显示模块TCl602A与单片机的接口技术J 国外电子元器件,2003.8韩本华. IC卡读写器J . 实用无线电,1992 ,(2).9沈红卫,等. IC 卡读写接口的可靠性设计 J . 自动化仪表,2000 ,(9)10姚潜镇低功耗射频IC卡读写器设计J今日电子，2006,(12)：90-9211董芳良浅谈公交IC卡读写器的应用及设计J. 大科技科技天地 , 2011(6)附录(外文文献)An Overview of AT89S51The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. Features：Compatible with MCS.-51 Products4K Bytes of In-System Programmable (ISP) Flash MemoryEndurance: 1000 Write/Erase Cycles4.0V to 5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHzThree-level Program Memory Lock128 x 8-bit Internal RAM32 Programmable I/O LinesTwo 16-bit Timer/CountersSix Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog TimerDual Data PointerPower-off FlagFast Programming TimeFlexible ISP Programming (Byte and Page Mode)Green (Pb/Halide-free) Packaging OptionThe AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.VCC：Supply voltage (all packages except 42-PDIP).GND：Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory).VDD：Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory.PWRVDD：Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage.PWRGND：Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground.Port 0：Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull-ups.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table.P3 port can also be used as a number of special features AT89C51 mouth, the following table:PinAlternative functionP3.0 RXD（Serial input）P3.1 TXD（Serial output）P3.2 （External interrupt 0）P3.3 （External interrupt 1）P3.4 T0（Timer 0 External input）P3.5 T1（Timer 1 External input）P3.6 （External data memory write strobe）P3.7 （External data memory read strobe）RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifierSpecial Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1”during power up. It can be set and rest under software control and is not affected by reset.Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64Kbytes each of external Program and Data Memory can be addressed.Program Memory：If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.Data Memory：The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.Watchdog Timer (One-time Enabled with Reset-out)：The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register(SFR location OA6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.The use of watchdog (WDT):WDT to be open to write 01EH and 0E1H in sequence to WDTRST registers (SFRs address 0A6H), when the WDT opened, take some time to 01EH and 0E1H to WDTRST count register in order to avoid WDT overflow. WDT counter 14 count reached 16383 (3FFFH), WDT will overflow and reset the device. WDT is turned on, it will be with the crystal oscillator in each machine cycle count, which means that users must be less than 16,383 machines each cycle reset WDT, that is to write 01EH and 0E1H to WDTRST register, WDTRST write only register. WDT counter can not be read neither write, when the WDT overflows, it is usually RST pin will reset the output of high pulse. Reset pulse duration for the 98 Tosc, and Tosc = 1/Fosc (crystal oscillation frequency).In order to optimize the work WDT must be at the right time code WDT reset periodically to prevent the WDT overflow.（译文）单片机AT89S51的概述AT89S51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)也可用传统方法进行编程及通用8位微处理器于单片芯片中，ATMEL公司的功能强大，低价位AT89S51单片机可为您提供许多高性价比的应用场介，可灵活应用于各种控制领域。主要性能参数：与MCS-51 产品指令系统完全兼容4k字节在线系统编程(ISP) Flash闪速存储器1000次擦写周期4.0-5.5V的工作电压范围全静态工作模式：0Hz-33MHz三级程序加密锁1288字节内部RAM32个可编程I/O口线2个16位定时/计数器6个中断源全双工串行UART通道低功耗空闲和掉电模式中断可从空闲模式唤醒系统看门狗(WDT)及双数据指针掉电标识和快速编程特性灵活的在线系统编程(ISP一字节或页写模式)功能特性概述：AT89S51提供以下标准功能：4k字节Flash闪速存储器，128字节内部RAM， 32个I/O口线，看门狗（WDT），两个数据指针，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89S51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。引脚功能说明：Vcc： 电源电压GND：地P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能驱动8个TTL逻辑门电路，对端口写1可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址(低8位)和数据总线复用，在访问期间激活内部上拉电阻。在Flash编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写1，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。Flash编程和程序校验期间 P 1接收低8位地址。P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写1，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。在访问外部程序存储器或16位地址的外部数据存储器(例如执行MOVX DPTR指令)时，P2口送出高 8位地址数据。在访问8位地址的外部数据存储器(如执行MOVX Ri指令)时，P2口线卜的内容(也即特殊功能寄存器（SFR)区中P2寄存器的内容)，在整个访问期间不改变。Flash编程或校验时，P2亦接收高位地址和其它控制信号。P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流（In）。 P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能。P3 口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。P3口也可作为AT89C51的一些特殊功能口，如下表所示：管脚备选功能P3.0 RXD（串行输入口）P3.1 TXD（串行输出口）P3.2 （外部中断0）P3.3 （外部中断1）P3.4 T0（记时器0外部输入）P3.5 T1（记时器1外部输入）P3.6 （外部数据存储器写选通）P3.7 （外部数据存储器读选通）RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。WDT溢出将使该引脚输出高电平，设置SFR AUXR 的DISRTO位（地址8EH）可打开或关闭该功能。DISRTO位缺省为RESET输出高电平打开状态。ALE/PROG：当访问外部程序存储器或数据存储器时，ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，囚此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR)区中的8EH单元的D0位置位，可禁正ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。PSEN：程序储存允许(PSEN)输出是外部程序存储器的读选通信号，当AT89S51由外部程序存储器取指令(数据)时，每个机器周期两次PSEN有效，即输出两个脉冲。当访问外部数据存储器，没有两次有效的PSEN信号。EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器(地址为0000H-FFFFH), EA端必须保持低电平(接地)。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如EA端为高电平(接Vcc端)，CPU则执行内部程序存储器中的指令。Flash存储器编程时，该引脚加上+12 V的编程电压Vpp。XTAL 1：振荡器反相放大器及内部时钟发生器的输入端。XTAL2：振荡器反相放大器的输出端。特殊功能寄存器：特殊功能寄存器的于片内的空间分布的这些地址并没有全部占用，没有占用的地址亦不可使用，读这些地址将得到一个随意的数值。而写这些地址单元将不能得到预期的结果。中断寄存器：各中断允许控制位于IE寄存器，5个中断源的中断优先级控制位于IP寄存器。双时钟指针寄存器：为更方便地访问内部和外部数据存储器，提供了两个16位数据指针寄存器：DP0位于SFR(特殊功能寄存器)区块中的地址82H, 83H和DP1位于地址84H, 85H，当SFR中的位DPS=0选择DP0，而DPS=1则选择DP1。用户应在访问相应的数据指针寄存器前初始化DPS位。电源空闲标志：电源空闲标志（POF）在特殊功能寄存器SFR中PCON的第4位(PCON.4，电源打开时POF置1，它可由软件设置睡眠状态并不为复位所影响。程序存储器：如果EA引脚接地(GND)，全部程序均执行外部存储器。在AT89S51,假如EA接至Vcc(电源+)，程序首先执行地址从0000H-OFFFH （4KB）内部程序存储器，而执行地址为1000H-FFFFH (60KB)的外部程序存储器。 数据存储器：AT89S51的具有128字节的内部RAM，这128字节可利用直接或间接寻址方式访问，堆栈操作