程序设计.doc

.设计一个“01111110”序列检测器，采用VHDL语言编写。2.设计一4-2编码器（10分）3.设计一异步复位、模60计数器（10分）4.试编写“01111110”序列发生器的VHDL语言程序。5.采用VHDL语言描述该电路6.编写16选1数据选择器的VHDL源程序。设电路的16位数据输入为A15.0，使能控制端为ENA，高电平有效，数据选择输出为Y。7.编写8位二进制数据比较器的VHDL源程序。设电路的两个8位二进制输入为A7.0和B7.0，当A7.0B7.0是时输出GT=1, 当A7.0B7.0是时输出LT=1, 当A7.0=B7.0是时输出EQ=1。8.采用VHDL语言描述该电路。9.下表为双向数据缓冲器的功能表，根据该功能表采用VHDL语言编写双向数据缓冲器（a位宽8）。EnDr功能00a=b01b=a1X三态10.采用VHDL语言描述该电路11.编写程序（10分） 试编写上升沿触发的D触发器的VHDL语言程序。12.编写程序（10分）试编写下降沿触发的D触发器的VHDL语言程序。答案1.library IEEE;use IEEE.STD_LOGIC_1164.all;entity rplcont is port( clk,rst,datain : in STD_LOGIC; q : out STD_LOGIC); end rplcont;architecture rplcont of rplcont istype states is (st0,st1,st2,st3,st4,st5,st6,st7,st8);signal cur_state,next_state : states;beginprocess(clk,rst)begin if rst=1 then cur_state=st0; elsif clkevent and clk=1 then cur_state=next_state; end if; end process;process(cur_state,next_state) begin q if datain=0 then next_state=st1; else next_state if datain=1 then next_state=st2; else next_state if datain=1 then next_state=st3; else next_state if datain=1 then next_state=st4; else next_stateif datain=1 then next_state=st5; else next_stateif datain=1 then next_state=st6; else next_stateif datain=1 then next_state=st7; else next_stateif datain=0 then next_state=st8; q=1; else next_state if datain=0 then next_state=st1; else next_state=st2; end if; end case;end process; end rplcont;2.设计一4-2编码器（10分）library ieee;use ieee.std_logic_1164.all;entity code4 is port( a,b,c,d : in std_logic; y0,y1 : out std_logic );end code4;architecture code4 of code4 issignal ddd:std_logic_vector(3 downto 0); signal q:std_logic_vector(1 downto 0);beginddd=a&b&c&d;process(d)begin if (ddd(0)=0) then q = 11; elsif (ddd(1)=0) then q = 10; elsif(ddd(2)=0) then q=01; else q = 00;end if;end process;y1=q(0);y0=q(1);end code4;3.设计一异步复位、模60计数器（10分）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt60 is port( clk,rst : in std_logic; m60 : out std_logic_vector(5 downto 0) );end cnt60;architecture cnt60 of cnt60 issignal cnt60:std_logic_vector(5 downto 0); beginprocess(clk,rst)begin if rst=1 then cnt600); elsif clkevent and clk=1 then if cnt60=59 then cnt600); else cnt60= cnt60+1; end if;end if;end process;m60=cnt60;end cnt60;4. library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity rplcont is port( clk,rst : in STD_LOGIC; zo : out STD_LOGIC); end rplcont;architecture rplcont of rplcont issignal count:std_logic_vector(2 downto 0);signal z:std_logic;beginprocess(clk,rst) begin if rst=1 then count=000; elsif clkevent and clk=1 then if count=7 then count=000; else countzzzzzzzz=0; end case; end process; process(rst,clk) begin if rst=1 then zo=0; elsif clkevent and clk=1 then zo=z; end if; end process; end rplcont;5.程序如下library IEEE;use IEEE.STD_LOGIC_1164.all;entity rplcont is port( clk : in STD_LOGIC; count : out STD_LOGIC_VECTOR(7 downto 0); end rplcont;architecture rplcont of rplcont issignal count_in_bar:std_logic_vector(7 downto 0);component dffport (clk,d:in std_logic; q,qb:out std_logic);end component ;begin count_in_bar(0)count_in_bar(i), d=count_in_bar(i+1), q=count(i),qb=count_in_bar(i+1); end generate;end rplcont;6.程序如下library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux16_1 isport( s3,s2,s1,s0: in std_logic;d15,d14,d13,d12: in std_logic; d11,d10,d9,d8: in std_logic; d7,d6,d5,d4: in std_logic; d3,d2,d1,d0: in std_logic; y: out std_logic);end mux16_1;architecture one of mux16_1 issignal s: std_logic_vector(3 downto 0); begin s=s3&s2&s1&s0; yb then gt=1; lt=0; eq=0; elsif ab then lt=1;gt=0;eq=0; else lt=0;gt=0; eqb7.0时，输出GT=1（表示a大于b），当a7.0b7.0时，输出lT=1（表示a小于b），当a7.0=b7.0时，输出EQ=1（表示a等于b）。8程序如下architecture shift of shift isbegincomponent dffport (d,clk: in std_logic;q: out std_logic);end component ;signal z:std_logic_vector(0 to 4);beginz(0)=a;g1:for i in 0 to 3 generate dffx:dff port map (z(i),clk,z(i+1);end generate;b=z(4);end shift;9程序如下library IEEE;use IEEE.STD_LOGIC_1164.all;entity buffer is port( a,b : inout STD_LOGIC_vector(7 downto 0); en,dr : in STD_LOGIC);end buffer;architecture buffer of buffer r issignal aout,bout: STD_LOGIC_vector(7 downto 0);begin process(a,dr,en)beginif en=0 and dr=1 thenbout=a;elsebout=ZZZZZZZZ;end if;b=bout;end process;process(a,dr,en)beginif en=0 and dr=0 thenaout=b;elseaout=ZZZZZZZZ;end if;a=aout;end process;end buffer; 10. 程序如下library IEEE;use IEEE.STD_LOGIC_1164.all;entity half_adder is port( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; co : out STD_LOGIC );end half_adder;architecture half_adder of half_adder issignal c,d:std_logic;begin c=a or b; d=a nand b; co=not d; s=c and d;end half_adder;library IEEE;use IEEE.STD_LOGIC_1164.all;entity full_adder is port( a,b,cin : in STD_LOGIC; co,s : out STD_LOGIC);end full_adder;architecture full_adder of full_adder iscomponent half_adderport( a,b : in STD_LOGIC; s,co : out STD_LOGIC );end component ;signal u0_co,u0_s,u1_co:std_logic;begin u0:half_adder port map(a,b,u0_s,u0_co); u1:half_adder port map(u0_s,b,cin,s,u1_co); co=u0_co or u1_co;end full_adder;11.编写程序试编写上升沿触发的D触发器的VHDL语言程序。LIBRARY IEEE;USE IEEE.std_logic_1164.all ;ENTITY sels IS PORT(d，clk:IN STD_LOGIC; q, n