DE2 实验练习解答—lab 2：数字和显示(digital Logic)(DE2).doc

/halflife/archive/2010/04/23/1718797.html本节练习主要用组合逻辑电路实现2进制到10进制数字的转换以及BCD码的加法。Part I 2进制数字的显示在HEX3到HEX0上显示SW15-0的值。SW15-12，SW11-8，SW7-4，SW3-0分别对应于HEX3，HEX2，HEX1，HEX0.在数码管上显示0-9，忽略开关表示的数值1010-1111.本练习的目的是手工推导数码管显示的逻辑，要求只用赋值语句和布尔表达式实现。.part1顶层文件 1 /part1 display 0-9 on the 7-segment displays 2 module part1(HEX3,HEX2,HEX1,HEX0,SW); 3 input 15:0SW; 4 output 0:6HEX3,HEX2,HEX1,HEX0; 5 6 btd H3(SW15:12,HEX3); 7 btd H2(SW11:8,HEX2); 8 btd H1(SW7:4,HEX1); 9 btd H0(SW3:0,HEX0);10 11 endmodule数码管译码电路： 1 /binary-to-decimal 2 module btd(s,seg); 3 input 3:0s; 4 output 0:6seg; 5 6 assign seg6=s3&s2&s1|s2&s1&s0; 7 assign seg5=s3&s2&s0|s2&s1|s1&s0; 8 assign seg4=s0|s2&s1; 9 assign seg3=s3&s2&s1&s0|10 s2&s1&s0|11 s2&s1&s0;12 assign seg2=s2&s1&s0;13 assign seg1=s2&s1&s0|s2&s1&s0;14 assign seg0=s2&s1&s0|s3&s2&s1&s0;15 16 endmodule 进制值转换为进制将位二进制输入转换成位十进制数，在和上分别显示和.输出值与输入值的对应关系如表.图给出了电路的部分设计。比较器用来检测电路用来将的输入转换成对应的个位的码电路用来将位二进制的输入转换为对应的码显示. 1 /part 2 2 module part2(V,D1,D0); 3 input 3:0V; 4 output 0:6D1,D0; 5 wire z; /comparator output 6 wire 2:0a; /circuit A output 7 wire 3:0m; /multiplexer output 8 9 comparator C(V,z);10 circuita A(V2:0,a);11 mux_4b_2to1 M(V,1b0,a,z,m);12 circuitb B(z,D1);13 btd D(m,D0);14 15 endmodule 16 17 /circuit B18 module circuitb(z,seg);19 input z;20 output 0:6seg;21 22 assign seg6=1;23 assign seg5=z;24 assign seg4=z;25 assign seg3=z;26 assign seg2=0;27 assign seg1=0;28 assign seg0=z;29 30 endmodule31 32 33 /4-bit 2-to-1 multiplexer34 module mux_4b_2to1(x,y,s,m);35 input 3:0x;36 input 3:0y;37 input s;38 output 3:0m;39 40 mux_2to1 u3(x3,y3,s,m3);41 mux_2to1 u2(x2,y2,s,m2);42 mux_2to1 u1(x1,y1,s,m1);43 mux_2to1 u0(x0,y0,s,m0);44 45 endmodule 46 /2to1 multiplexer47 module mux_2to1(a,b,s,m);48 input a,b,s;49 output m;50 51 assign m=s?b:a;52 53 endmodule 54 55 56 /circuit A57 module circuita(v,a);58 input 2:0v;59 output 2:0a;60 61 assign a2=v2&v1;62 assign a1=v2&v1;63 assign a0=(v1&v0)|(v2&v0);64 65 endmodule行波进位加法器. 1 /4-bit ripple-carry adder circuit 2 module part3(SW,LEDR,LEDG); 3 input 8:0SW; 4 output 8:0LEDR; 5 output 4:0LEDG; 6 wire 3:0a,b; 7 wire cin; 8 wire 3:0s; 9 wire cout;10 wire 3:1c;11 12 assign LEDR=SW;13 assign cin=SW8;14 assign a=SW7:4;15 assign b=SW3:0;16 assign LEDG4=cout;17 assign LEDG3:0=s;18 19 fadder(cin,a0,b0,s0,c1);20 fadder(c1,a1,b1,s1,c2);21 fadder(c2,a2,b2,s2,c3);22 fadder(c3,a3,b3,s3,cout);23 24 endmodule25 26 /full adder27 module fadder(ci,a,b,s,co);28 input ci,a,b;29 output s,co;30 31 assign s=ciab,32 co=(ab)?ci:b;33 34 endmodule 位加法器注意处理和的最大值+。. 1 /part IV:BCD adder 2 3 /circuit A 4 module circuit_A(s,ao); 5 input 3:0s; 6 output 3:0ao; 7 8 assign ao3=s3&s2&s1, 9 ao2=(s3&s2&s1)|(s3&s2&s1), 10 ao1=(s3&s2&s1)|(s3&s2&s1), 11 ao0=(s3&s2&s0)|(s3&s2&s0)| 12 (s2&s1&s0); 13 14 endmodule 15 16 /4-bit 2-to-1 multiplexer 17 module mux2to1_4b(x,y,s,m); 18 input 3:0x,y; 19 input s; 20 output 3:0m; 21 22 mux_2to1 u3(x3,y3,s,m3); 23 mux_2to1 u2(x2,y2,s,m2); 24 mux_2to1 u1(x1,y1,s,m1); 25 mux_2to1 u0(x0,y0,s,m0); 26 27 endmodule 28 /2to1 multiplexer 29 module mux_2to1(a,b,s,m); 30 input a,b,s; 31 output m; 32 33 assign m=s?b:a; 34 35 endmodule 36 37 /circuit B 38 module circuit_B(z,seg); 39 input z; 40 output 0:6seg; 41 42 assign seg6=1; 43 assign seg5=z; 44 assign seg4=z; 45 assign seg3=z; 46 assign seg2=0; 47 assign seg1=0; 48 assign seg0=z; 49 50 endmodule 51 52 /7-segment decoder 53 module btd(s,seg); 54 input 3:0s; 55 output 0:6seg; 56 57 assign seg6=s3&s2&s1|s2&s1&s0; 58 assign seg5=s3&s2&s0|s2&s1|s1&s0; 59 assign seg4=s0|s2&s1; 60 assign seg3=s3&s2&s1&s0| 61 s2&s1&s0| 62 s2&s1&s0; 63 assign seg2=s2&s1&s0; 64 assign seg1=s2&s1&s0|s2&s1&s0; 65 assign seg0=s2&s1&s0|s3&s2&s1&s0; 66 67 endmodule 68 69 /4-bit full adder 70 module fa_4b(a,b,s,cin,cout); 71 input 3:0a,b; 72 input cin; 73 output 3:0s; 74 output cout; 75 76 wire 3:1c; 77 78 fadder fao(cin,a0,b0,s0,c1); 79 fadder fa1(c1,a1,b1,s1,c2); 80 fadder fa2(c2,a2,b2,s2,c3); 81 fadder fa3(c3,a3,b3,s3,cout); 82 83 endmodule 84 85 /full adder 86 module fadder(ci,a,b,s,co); 87 input ci,a,b; 88 output s,co; 89 90 assign s=ciab, 91 co=(ab)?ci:b; 92 93 endmodule 94 95 /circuit comparator 96 module comparator(v,z); 97 input 3:0v; 98 output z; 99 100 assign z=(v3&v2)|(v3&v1);101 102 endmodule 103 104 /part 4 top file105 module part4(SW,LEDR,LEDG,LEDG8,HEX6,HEX4,HEX1,HEX0);106 input 8:0SW; /Cin,A,B107 output 8:0LEDR;108 output 4:0LEDG;109 output 0:6HEX6,HEX4,HEX1,HEX0;110 output LEDG8;111 112 wire 3:0sum; /sum113 wire co; /cout114 wire 3:0ao; /circuit_A output115 wire 3:0m; /mux2to1_4b output116 wire z; /comparator output117 wire bi; /circuit_B input118 wire va,vb; /A,B comparator output119 assign LEDR=SW,120 LEDG4=co,121 LEDG3:0=sum,122 LEDG8=va|vb;123 assign bi=co|z; 124 125 fa_4b u0(SW7:4,SW3:0,sum,SW8,co);126 circuit_A u1(sum,ao);127 comparator u7(sum,z);128 mux2to1_4b u2(sum,ao,bi,m);129 btd u3(m,HEX0);130 circuit_B u4(bi,HEX1);131 btd u5(SW7:4,HEX6);132 btd u6(SW3:0,HEX4);133 comparator u8(SW7:4,va),134 u9(SW3:0,vb);135 136 137 138 endmodule 139 位加法器. 1 /*.The ADDER CIRUIT.*/ 2 /A Full Adder Circuit 3 module fulladder(C,A,B,S,O); 4 input C,A,B; 5 output S,O; 6 7 /C = CarryIn, A & B = Inputs, S = Sum, O = Carryout 8 assign S = C(AB); 9 assign O = (AB)&B)|(AB)&C);10 endmodule11 12 /4 Bit, Full Adder Circuit13 module fulladder_4bit(C,A,B,S,O);14 input C;15 input 3:0A,B;16 output O;17 output 3:0S;18 wire 3:0cwire;19 20 /C=CarryIn, A&B = Inputs, S = Sumb, O = CarryOut, CWIRE= Carry wire between adders21 fulladder N0(C,A0,B0,S0,cwire0);22 fulladder N1(cwire0,A1,B1,S1,cwire1);23 fulladder N2(cwire1,A2,B2,S2,cwire2);24 fulladder N3(cwire2,A3,B3,S3,cwire3);25 26 /BCD Carry27 assign O = cwire3|(S3&S2)|(S3&S1);28 endmodule29 30 /BCD Adder: Sum Finder31 module bcdAdder(C,A,B,S,O);32 input C;33 input 3:0A,B;34 output 3:0S;35 output O;36 wire 3:0cwire;37 wire 3:0preSum;38 39 fulladder_4bit MidAd1(C,A,B,preSum,O);40 41 assign cwire0 = 0;42 assign cwire1 = O;43 assign cwire2 = O;44 assign cwire3 = 0;45 46 47 fulladder_4bit MidAd2(0,cwire,preSum,S);48 49 endmodule50 51 /top_level file52 module part5(SW,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,53 HEX0);54 input 16:0SW;55 output 0:6HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,56 HEX0;57 58 wire 3:0s0,s1;59 wire co0,co1;60 61 btd ua1(SW15:12,HEX7);62 btd ua0(SW11:8,HEX6);63 btd ub1(SW7:4,HEX5);64 btd ub0(SW3:0,HEX4);65 66 bcdAdder u0(SW16,SW11:8,SW3:0,s0,co0);67 bcdAdder u1(co0,SW15:12,SW7:4,s1,co1);68 circuit_B us2(co1,HEX2);69 btd us1(s1,HEX1);70 btd us0(s0,HEX0);71 72 endmodule 另种实现位加法器的方法用结构实现，抽象描述，让编译器去实现具体电路。. 1 /1-digit bcd_adder 2 module bcdadder(Ci,A,B,S,Co); 3 input Ci; 4 input 3:0A,B; 5 output reg 3:0S; 6 output reg Co; 7 8 reg 3:0z; 9 reg 4:0t;10 11 always (Ci,A,B)12 begin13 t=A+B+Ci;14 if(t9)15 begin16 z=4d10;17 Co=1b1;18 end19 else 20 begin21 z=0;22 Co=0;23 end24 S=t-z;25 end26 endmodule 27 28 /top_level file29 module bcdadder_2(SW,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,30 HEX0);31 input 16:0SW;32 output 0:6HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,33 HEX0;34 35 wire 3:0s0,s1;36 wire co0,co1;37 38 btd ua1(SW15:12,HEX7);39 btd ua0(SW11:8,HEX6);40 btd ub1(SW7:4,HEX5);41 btd ub0(SW3:0,HEX4);42 43 bcdadder u0(SW16,SW11:8,SW3:0,s0,co0);44 bcdadder u1(co0,SW15:12,SW7:4,s1,co1);45 circuit_B us2(co1,HEX2);46 btd us1(s1,HEX1);47 btd us0(s0,HEX0);48 49 endmodule 位二进制数转换为位十进制数的电路方法：用两个寄存器，一个bit，一个bit，分别存bin码和有待实现的bcd码。接下来，逐位将BIN的最高位移入BCD的最低位。同时，将BCD的16位寄存器按每四位划成一块，我们称之为个十百千好了。但记住，个，十，百，千都有4个bit位。 1.将bin（bin是bin:0）移入bcd0。这样，bin就变成了原来的bin，bin0=0。 2.分别检查个十百千里存的数是不是大于等于5（按二进制换十进制那样换算），如果是，加3。 3.重做1，2。直到全部移进去。 原理：bin和bcd的表示方法的差别，就在于10用bin表示为1010，用bcd表示成10000。但左移一位就是乘2，这个是没问题的。因此，如果不做2的操作，就等于不停的把个位数乘2加上新的个位数，这样还是原来的数。做了2之后，就等于把原来的1010变成10000，因为1010在bcd码里是不可能出现的，因此要把10变成bin下面的16。而5=10/2，3=（16-10）/2，也等于（18-12）/2等等等等。参考：BCD and Add3 Converter by Dr. John S. Loomis:/ece314/notes/devices/binary_to_BCD/bin_to_bcd.html . 1 /6-bit binary to 2-digit BCD 2 module b2b(a,ones,ten