流水灯VHDL.doc

-/*- * 文件: counter.vhd- * 模块: 计数器- * 版本： version 1.0- * - * 功能说明:- * 对输入时钟按照参数指定的最大值进行计数，并输出计数值- *- * 端口说明:- * 输出- * o - 每个输入时钟到来后加1，达到计数器模值UNIT-1后恢复为0- *- *输入- * i - 待计数的输入脉冲- * clk - 时钟- * rst - 复位信号，低电平有效- *- *双向- * 无- *- * 参数说明:- *UNIT - 计数器输出的最大值+1- *COUNTER_WIDTH - UNIT值位宽- *- * 变更记录: - * 2011/8/20. 新建- *- */library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity counter isgeneric(UNIT : integer := 16; -计数器模值COUNTER_WIDTH : integer := 4 -计数器位宽);port(o : out std_logic_vector(COUNTER_WIDTH-1 downto 0);i : in std_logic;clk : in std_logic;rst : in std_logic);end counter;architecture counter_architecture of counter is signal counter : std_logic_vector(COUNTER_WIDTH-1 downto 0); signal din_1 : std_logic; signal i_posedge : std_logic;begin o = counter;process(clk, rst)beginif (rst = 0) thendin_1 = 1;elsif(clkevent and clk = 0) theni_posedge = (not din_1) and i;din_1 = i;end if;-clkevent end process;process(clk, rst)beginif (rst = 0) thencounter 0);elsif(clkevent and clk = 1) then if (i_posedge = 1) then if (counter = UNIT-1) then counter 0); else counter = counter+1; end if; end if;end if;end process;end counter_architecture;-/*- * 文件: led_drv.vhd- * 模块: led驱动- * - * 功能说明:- * 将输入的4位二进制数转为8位可驱动led的二进制位。- * 端口说明:- * 输出参数- * led - 8位可驱动led的二进制位- *- *输入参数- * data - 4位二进制数- *- *双向- * 无- *- * 参数说明:- * 无- *- * 变更记录: - * , 新建- *- */library ieee;use ieee.std_logic_1164.all;entity led_drv isport(dat : in std_logic_vector(3 downto 0);led : out std_logic_vector(7 downto 0);end led_drv;architecture led_drv_architecture of led_drv isbegin with dat select led= 11111110 when 0000, 11111101 when 0001, 11111011 when 0010, 11110111 when 0011, 11101111 when 0100, 11011111 when 0101, 10111111 when 0110, 01111111 when 0111, 11111100 when 1000, 11110011 when 1001, 11001111 when 1010, 00111111 when 1011, 11110000 when 1100, 00001111 when 1101, 00000000 when 1110, 11111111 when 1111, 11111111 when others;end led_drv_architecture;-/*- * 文件: div_sim.vhd- * 模块: 分频器- * - * 功能说明:- * 对输入时钟按照参数指定的分频系数进行分频输出- *- * 端口说明:- * 输出- * o - 分频输出，它的频率由输入时钟和分频系数确定:o = i/DIV_FACTOR- *- *输入- * clk - 时钟- * rst - 复位信号，低电平有效- *- *双向- * 无- *- * 参数说明:- *DIV_FACTOR - 分频系数，o = clk/DIV_FACTOR- *- * 变更记录: - * - *- */library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity div_sim isgeneric(DIV_FACTOR : integer := 16 -分频比);port(o : out std_logic;clk : in std_logic;rst : in std_logic);end div_sim;architecture divisor_architecture of div_sim is signal counter : integer range 0 to DIV_FACTOR-1;begin o = 1 when(counterDIV_FACTOR/2) else 0;process(clk, rst)beginif (rst = 0) thencounter = 0;elsif(clkevent