STM8-SWIM通信协议和调试模块用户手册(部分翻译).pdf

翻译 本人应朋友之邀 翻译了本文的第三章 由于水平有限 且没有用过STM8系列的控制器 如有错误 请见 谅 by踏雪无痕 2010 11 11 rose yiyong December 2009Doc ID 14024 Rev 21 37 UM0470 User manual STM8 SWIM communication protocol and debug module Introduction This manual has been written for developers who need to build programming testing or debugging tools for the STM8 microcontroller family It explains the debug architecture of the STM8 core The STM8 debug system consists of two modules DM Debug module SWIM Single wire interface module Related documentation STM8S Flash programming reference manual PM0051 STM8L Flash programming manual PM0054 STM8 SWIM 通信协议和调试模块用户手册 1 介绍 STM8微控制器家族的测试或调试工具 它解释了 s t m 8 内核调试体系结构 STM8 调试系统由两个模块组成 调试模块 单线接口模块 叙述文档 ContentsUM0470 2 37Doc ID 14024 Rev 2 Contents 1Debug system overview 6 2Communication layer 7 3Single wire interface module SWIM 8 3 1Operating modes 8 3 2SWIM entry sequence 9 3 3Bit format 11 3 3 1High speed bit format 11 3 3 2Low speed bit format 12 3 4SWIM communication protocol 13 3 5SWIM commands 14 3 5 1SRST system reset 14 3 5 2ROTF read on the fly 14 3 5 3WOTF write on the fly 15 3 6SWIM communication reset 15 3 7CPU register access 16 3 8SWIM communication in Halt mode 16 3 9Physical layer 17 3 10STM8 SWIM registers 18 3 10 1SWIM control status register SWIM CSR 18 3 10 2SWIM clock control register CLK SWIMCCR 19 4Debug module DM 20 4 1Introduction 20 4 2Main features 20 4 3Debug 22 4 3 1Reset 22 4 3 2Breakpoints 22 4 3 3Abort 22 4 3 4Watchdog control 22 4 3 5Interaction with SWIM 22 4 4Breakpoint decoding table 23 UM0470Contents Doc ID 14024 Rev 23 37 4 5Software breakpoint mode 24 4 6Timing description 24 4 7Abort 24 4 8Data breakpoint 25 4 9Instruction breakpoint 25 4 10Step mode 25 4 11Application notes 26 4 11 1Illegal Memory access 26 4 11 2Forbidden stack access 26 4 11 3DM break 26 4 12DM registers 27 4 12 1DM breakpoint register 1 extended byte DM BKR1E 27 4 12 2DM breakpoint register 1 high byte DM BKR1H 27 4 12 3DM breakpoint register 1 low byte DM BKR1L 27 4 12 4DM breakpoint register 2 extended byte DM BKR2E 28 4 12 5DM breakpoint register 2 high byte DM BKR2H 28 4 12 6DM breakpoint register 2 low byte DM BKR2L 28 4 12 7DM control register 1 DM CR1 29 4 12 8DM control register 2 DM CR2 30 4 12 9DM control status register 1 DM CSR1 31 4 12 10DM control status register 2 DM CSR2 32 4 12 11DM enable function register DM ENFCTR 33 4 12 12Summary of SWIM DM and core register maps 34 Appendix ADescription of the DM ENFCTR register for each STM8 product 35 Revision history 36 List of tablesUM0470 4 37Doc ID 14024 Rev 2 List of tables Table 1 SWIM command summary 14 Table 2 CPU register memory mapping in STM8 16 Table 3 SWIM pin characteristics 17 Table 4 Decoding table for breakpoint interrupt generation 23 Table 5 STM8 registers 34 Table 6 Peripherals which are frozen by the bits of the DM ENFCTR register for each STM8 product 35 Table 7 Document revision history 36 UM0470List of figures Doc ID 14024 Rev 25 37 List of figures Figure 1 Debug system block diagram 6 Figure 2 SWIM pin external connections 7 Figure 3 SWIM activation sequence 8 Figure 4 SWIM activation timing diagram 9 Figure 5 SWIM entry sequence 10 Figure 6 High speed bit format 11 Figure 7 Low speed bit format 12 Figure 8 Command format Host Target 13 Figure 9 Data format Target Host 13 Figure 10 Timings on SWIM pin 17 Figure 11 Debug module block diagram 21 Figure 12 STM8 Instruction Model 24 Figure 13 STM8 Debug Module Stall Timing 24 Figure 14 STM8 DM Data Break Timing 25 Figure 15 STM8 DM instruction break timing 25 Figure 16 STM8 DM step timing 25 Debug system overviewUM0470 6 37Doc ID 14024 Rev 2 1 Debug system overview The STM8 debug system interface allows a debugging or programming tool to be connected to the MCU through a single wire bidirectional communication based on open drain line It provides non intrusive read write access to RAM and peripherals during program execution The block diagram is shown in Figure 1 Figure 1 Debug system block diagram The debug module uses the two internal clock sources present in the device the LSI Low Speed Internal clock usually in the range 30 kHz 200 kHz depending on the product one and the HSI High Speed Internal clock usually in the range 10 MHz to 25 MHz depending on the device The clocks are automatically started when necessary SWIM Entry LSI oscillator HSI oscillator Comm Layer Command Decode Debug module DM STM8 Core Peripherals SWIM pin Peripheral Bus CPU Bus SWIM RAM Flash RAM Bus STM8 Data EEPROM 调试系统总览 UM0470Communication layer Doc ID 14024 Rev 27 37 2 Communication layer The SWIM is a single wire interface based on asynchronous high sink 8 mA open drain bidirectional communication While the CPU is running the SWIM allows non intrusive read write accesses to be performed on the fly to the RAM and peripheral registers for debug purposes In addition while the CPU is stalled the SWIM allows read write accesses to be performed to any other part of the MCU s memory space Data EEPROM and program memory CPU registers A X Y CC SP can also be accessed These registers are mapped in memory and can be accessed in the same way as other memory addresses Register peripherals and memory can be accessed only when the SWIM DM bit is set When the system is in HALT WFI or readout protection mode the NO ACCESS flag in the SWIM CSR register is set In this case it is forbidden to perform any accesses because parts of the device may not be clocked and a read access could return garbage or a write access might not succeed The SWIM can perform a MCU device software reset The SWIM pin can also be used by the MCU target application as a standard I O port with some restrictions if you also want to use it for debug The safest way is to provide a strap option on the application PCB Figure 2 SWIM pin external connections STM8 Application I O SWIM interface for tools Jumper selection for debug purposes SWIM pin 通信层 即使CPU在运行 SWIM 允许不插入读取访问执行空中飞入 o n t h e f l y 到RAM和外设寄存器达到调试目的 另外 当CPU停止时 SWIM允许读写MCU的其它部件的内存空间 DATA EEPROM 和 程序存储器 CPU 寄存器 A X Y CC SP 同样能读写 这些寄存器映射到内存并且能像 访问其它内存地址一样访问它们 寄存器 外设和内存只有在SWIM DM位设置时能读写 当系统在HALT WFI或者读出保护模式时 NO ACCESS 标志位 SWIM CSR 中 置位 既然这样 它禁止执行任何读写操作 因为这个部件可能没有 时钟 读操作会返回一个无效数据 写操作不能成功 SWIM能执行MCU的软件复位 SWIM引脚能像标准I O口一样供目标应用程序使用 但有一些限制 如果你要 在调试时使用 SWIM有最高优先级 你应该在应用的PCB上设置选项 如下图所 示 Single wire interface module SWIM UM0470 8 37Doc ID 14024 Rev 2 3 Single wire interface module SWIM 3 1 Operating modes After a Power On Reset powering of the device the SWIM is reset and enters in its OFF mode 1 OFF In this mode the SWIM pin must not be used as an I O by the application It is waiting for the SWIM entry sequence or to be switched to I O mode by the application software 2 I O This state is entered by the software application by setting the IOM bit in the core configuration register MCR In this state the user application can use the SWIM pin as a standard I O pin the only drawback is that there is no way to debug the functionality of this pin with the built in debug capabilities In case of a reset the SWIM goes back to OFF mode 3 ACTIVE This mode is entered when a specific sequence is detected on the SWIM pin while in OFF state In this state the SWIM pin is used by the host tool to control the STM8 with 3 commands SRST System Reset ROTF Read On The Fly WOTF Write On The Fly Note Please note that the SWIM can be set Active and communicate while the device is in RESET state NRST pin forced low Figure 3 SWIM activation sequence POR ACTIVE I O OFF IOM bit set Y SWIM entry sequence Y ROTFWOTF RST bit set reset N N Y N CSR SRST 单总线通信接口模块 工作模式 在上电复位时SWIM 复位并进入OFF模式 在这个模式下 SW IM 脚不能被任务程序用 作I O 它将等待SW I M 进入序列或者由 应用 软 件切换到I O 模式 I O 应用 程序可以置位内核配置寄存器 M CR 的I O M 位来进入这个模式 在这个模式 下 用 户程序可以将SW I M 管脚用 作标准I O 管脚 唯一的缺点是无法使用 内建的调试器来 调试这个管脚的功能 一旦复位 SW I M 将返回O FF模式 A CT IVE 在O FF模式下 当SW I M 管脚上检测到一个特 定的脉冲序列时 SW I M 将进入 A CT IVE模式 在这个模式下 SW I M 管脚将被主机通过三条命令来控制ST M 8 SRST 系 统复位 RO T F飞速读 W O T F飞速写 注意SW I M 只有设备在RESET 状 态下才可以被设置为A CT I VE模式和通信 NRST 管脚强制为低 UM0470Single wire interface module SWIM Doc ID 14024 Rev 29 37 3 2 SWIM entry sequence After a POR and as long as the SWIM is in OFF mode the SWIM pin is sampled for entry sequence detection In order to do this the internal low speed RC clock is automatically turned ON after POR and remains forced ON as long as the SWIM is in OFF mode If the register which forces the SWIM in I O mode is written before the entry sequence is finalized the SWIM enters I O mode Once the SWIM is ACTIVE writing this bit has no influence on communication and the SWIM interface remains in ACTIVE mode If an application uses the SWIM pin as standard I O it puts the SWIM interface in I O mode in the initialization section of the software code typically this is performed just after the reset However even in this case it is still possible to put the SWIM interface in ACTIVE mode by forcing the RESET pin to 0 and keep it low for the duration of the SWIM entry sequence As long as the SWIM is in OFF mode the SWIM entry sequence is detected at any moment during reset or when the application is running If both the SWIM pin and the reset pin are multiplexed with I Os the way to enter SWIM ACTIVE state is to power down the MCU device power up and to maintain the reset until the end of the SWIM entry sequence Figure 4 SWIM activation timing diagram SWIM 进入序列 上电 复位后 只要SW I M 处于O FF模式下 SW I M 管脚就会被采样 直到检测到进入序列 为 了达到这个目的 上电 复位后 只要SW I M 处于O FF模式下 内部低速RC时钟自动启动并强 制保持打开 如果在SW IM 检测到进入序列之前 配置SW I M 为I O 模式的寄存器被置位 则SW IM 进入I O 模式 一旦SW I M 进入A CT IVE模式 配置SW I M 为I O 模式为寄存器被置位也不影响通 信 SW I M 接口将保存在A CT I VE模式下 如果程序把SW I M 管脚作为标准I O 使用 则软件代码初始化部分就要将SW I M 接口配置为I O 模式 典型的是在复位之后 然而 即使在这种情况下 强制使RESET 脚为0 并保持为低直 到SW I M 进入序列完成 也可以使SW I M 模块进入A CT I VE模式 只要SW IM 在O FF模式下 SW IM 进入序列仍可以在任务时候被检测到 无论是复位期间还是 程序运行期间 如果SW I M 脚和r e s e t 脚都复用 为IO 则进入SW I M A CT I VE状 态的方法是使M CU 先掉电 再上电 来满足复位条件直到完成SW I M 的启动序列 Single wire interface module SWIM UM0470 10 37Doc ID 14024 Rev 2 SWIM activation is shown in Figure 4 and each segment on the diagram is described below 1 To make the SWIM active the SWIM pin must be forced low during a period of 16 s which is 64 pulses minimum at the frequency of HSI 2 After this first pulse at 0 the SWIM detects a specific sequence to guarantee robustness in the SWIM active state entry The SWIM entry sequence is 4 pulses at 1 kHz followed by 4 pulses at 2 kHz The frequency ratio is detected and allows SWIM entry The ratio can be easily detected whatever the internal RC frequency The waveform of the entry sequence is shown in Figure 5 Note that the sequence starts and ends with the SWIM pin at 1 3 After the entry sequence the SWIM enters in SWIM active state and the HSI oscillator is automatically turned ON 4 After this delay the SWIM sends a synchronization frame to the host Synchronization frame description A synchronization frame of 128 x HSI clock periods with the SWIM line at 0 is sent out by the MCU device to allow for the measurement of the RC by the debug host An advanced debug host can re calibrate its clock to adapt to the frequency of Internal RC 5 Before starting a SWIM communication the SWIM line must be released at 1 to guarantee that the SWIM is ready for communication at least 300 ns 6 Write 0A0h in the SWIM CSR setting bit 5 allows the whole memory range and SRST command to be accessed setting bit 7 masks the internal reset sources 7 Release reset which starts the option byte loading sequence Wait 1 ms for stabilization 8 Once option byte loading has occurred and stabilization time is reached the CPU is in phase 8 STM8S is stalled and HSI 16 Mhz see STM8S datasheets for accuracy SWIM clock is at HSI 2 8 Mhz SWIM is active in low speed bit format see Section 3 3 2 Figure 5 SWIM entry sequence SWIM pin SWIM Active 1 ms 500 s SWIM entry sequence SWIM 激活见每一个图表段的描述见下面 要使得SW I M 激活 SW IM 引脚必须保持低电 平至少16 u s 在第一个0 脉冲后 SW IM 检测到一个特 定的序列以保证SW I M 进入活动状 态 SW I M 的进入 脉冲序列为 4个频率 为1k H z 的脉冲 然后是4个频为1k H z 的脉冲 这些频率 检测到才允许 SW IM 进入 该比率 可以很容易地被检测到不管是任何的内部RC震荡频率 进入脉冲序 列的波形见图5 注意 这个序列启动和结束时SW I M 脚的电 平为1 即至少有H SI 中脉冲序列中的6 4个脉冲 在进入序列后 SW I M 进入SW I M 活动状 态 H SI 振荡器自动打开 在这段延时之后 SW I M 发送一个同步帧给主机 同步帧说明 1个同步帧为12 8 个H SI时钟 周期 M CU 置SW I M 线为0 电 平 允许调试主机测量RC振荡器 高级调试主机可以重复校 准它的时钟来适应M CU 内部RC震荡器的频率 SW IM 开始通信前 SW IM 线必须释放为1电 平来保证SW IM 已做好通人 准备 至少30 0 n s SW I M SCR写入0 x A 0 设置位5 使能整个内存空间和SRST 命令可以访问 设置位7 屏蔽内部复位源 释放r e s e t 置为低电 平 启动选项字节加载序列 等待1m s 后到达稳定状 态 一旦选项字节加载且稳定状 态时间达到 CPU 将进入阶段8 ST M 8 S 将暂停 H SI 16 M h z 见ST M 8 S数据表中的 精确性 SW I M 时钟为H SI 2 8 M h z SW IM 激活为低速位格式 见Se c t i o n 3 3 2 UM0470Single wire interface module SWIM Doc ID 14024 Rev 211 37 3 3 Bit format The bit format is a Return To Zero format which allows synchronization of every bit Two communication speeds are available At SWIM activation the low speed is selected The high speed is selected by setting the HS bit in the SWIM CSR register with the SWIM protocol When entering SWIM mode during the RESET phase it is possible that the option bytes have not yet been loaded from non volatile memory to their respective registers Option byte loading is triggered by any internal or external reset In order to ensure proper system behavior the HS bit should not be set until the option byte loading is finished At the end of the option byte loading the HSIT bit in the SWIM CSR is set by hardware 3 3 1 High speed bit format 1 bit is generated with ten HSI oscillator pulses The bit format is 2 pulses at 0 followed by 8 pulses at 1 for 1 value 8 pulses at 0 followed by 2 pulses at 1 for 0 value When the SWIM receives a data packet it will decode 1 when the number of consecutive samples at 0 is less or equal to 4 0 when the number of consecutive samples at 0 is greater or equal to 5 Figure 6 High speed bit format 1 0 位格式 位格式是一种回零格式 它允许任何一位为同步位 两种通信速率 在SW I M 激活时 为低速率 使用 SW I M 协议设置SW I M CSR寄存器的H S 位 使能高速率 D RESET 阶段期间进入SW I M 模式时 选项字节可以还没有从内存加载到它们各自的寄存 器中 任何内部或外部复位都会触发选项字节的加载 为了保证系统正确动作 H S位必须被置位 设置为1 直到选项字节加载完成 在选项 字节加载完成后 SW I M CSR寄存器的H SI T 位将将硬件置位 高速 位格式 10 个H SI 振荡周期产生 1位 位格式为 2 个0 脉冲后接着8 个1脉冲代表 1 8 个1脉冲后接着2 个0 脉冲代表 1 当SW I M 接收到一个数据包之后 它将自动解码 当连续采样到的0 脉冲的个数小于等于4 则解码为1 当连续采样到的0 脉冲的个数大于等于5 则解码为1 Single wire interface module SWIM UM0470 12 37Doc ID 14024 Rev 2 3 3 2 Low speed bit format 1 bit is generated with twenty two HSI oscillator pulses The bit format is 2 pulses at 0 followed by 20 pulses at 1 for 1 value 20 pulses at 0 followed by 2 pulses at 1 for 0 value When the SWIM receives a data packet it will decode 1 when the number of consecutive samples at 0 is less or equal to 8 0 when the number of consecutive samples at 0 is greater or equal to 9 Figure 7 Low speed bit format 1 0 低速 位格式 2 2 位H SI 振荡周期产生 1位 位格式为 2 个0 脉冲后接着2 0 个1脉冲代表 1 2 0 个1脉冲后接着2 个0 脉冲代表 1 当SW IM 接收到一个数据包之后 它将自动解码 当连续采样到的0 脉冲的个数小于等于8 则解码为1 当连续采样到的0 脉冲的个数大于等于9 则解码为1 UM0470Single wire interface module SWIM Doc ID 14024 Rev 213 37 3 4 SWIM communication protocol When in ACTIVE mode communication can be initiated by host or device Each byte or command is preceded by a 1 bit header in order to arbitrate if both host and device initiate the communication at the same time The host header is 0 in order to have the priority over the device in case of arbitration due to open drain capability The host can start the transfer only if there is no transfer on going Figure 8 Command format Host Target Each command sent by the host is made of 1 command ROTF WOTF or SWRST made of Header 1 bit at 0 b2 b0 3 bit command pb parity bit XOR between all b i ack acknowledge 1 bit at 1 The receiver must send the not acknowledge value if it has detected a parity error NACK not acknowledge 1 bit at 0 or it is not yet ready optionally several data packets in case of WOTF made of Header 1 bit at 0 b7 b0 8 bit data pb parity bit sent after data XOR between all b i ack acknowledge Figure 9 Data format Target Host Each data frame is made of Header 1 bit at 1 b7 b0 8 bit data pb parity bit sent after data ack acknowledge b2b1b0ack Command 0pb Data1 b7b6b5b4b3b2b1b0pb ack 0 Italic Bit sent by the Host Bold Bit sent by the device b7b6b5b4b3b2b1b0pb ack data ndata n 1 1 data n 1 Italic Bit sent by the Host Bold Bit sent by the device SWIM 通讯协议 在A CT I VE模式下 主机和设备都可以发起通信 每个字节前都加入1个起始位以仲裁主机和 设备同时开始通信 主机的起始位为0 使得发生 仲裁冲突时 与从机相比主机拥有优先权 由 于开漏性能 仅仅没有传输正在进行的时候 设备才可以启动转传输 每一条主机发送的命令的组成如下 1条命令 RO T F W O T F或者SW RST 组成如下 起始位 0 b 2 b 0 3位命令 p b 奇偶校验位 XO R 所有的位b 2 b 0 异或 a c k 应答位 1 检测到奇偶校验出错或者接收没有准备好时 接收者必须发送0 应答位 的值 可选的若干数据包 在W O T F命令时 组成如下 起始位 0 b 7 b 0 8 位数据 p b 奇偶校验位 XO R 所有的位b 7 b 0 异或 a c k 应答位 数据格式 目标到主机 起始位 1 b 7 b 0 数据位 p b 校验位 紧随数据位发送 a c k 应答位 Single wire interface module SWIM UM0470 14 37Doc ID 14024 Rev 2 3 5 SWIM commands The Host can send a command when the line is idle or after each data byte from device After sending the command the host releases the line When the SWIM is ready to answer to the command it initiates the transfer If a new command from the host occurs while a command is pending in SWIM the pending command is cancelled and the new command is decoded except in case of WOTF Three commands are available They are listed in Table 1 3 5 1 SRST system reset Format 1 command from Host to Target Parameters None SRST command generates a system reset only if SWIM CSR SWIM DM bit is set 3 5 2 ROTF read on the fly Format 1 command followed by the number of bytes to be read followed by the address on three bytes Parameters N The 8 bits are the number of bytes to read from 1 to 255 E H L This is the 24 bit address to be accessed D These are the data bytes read from the memory space If the host sends a NACK to a data byte the device will send the same byte again If SWIM DM bit is cleared ROTF can only be done on SWIM internal registers Table 1 SWIM command summary CommandBinary Code SRST000 ROTF001 WOTF010 Reserved for future use 011 1xx SRST ROTFN E H LD D N SW I M 命令字 当总线空闲或者设备发送完所有数据时 主机可以发送命令字 发送完命令字后 主要将释 放总线 当SW I M 准备好响应命令时 它会初始化传输 当SW I M 中有一条命令预备好时 如果此时接收到主机一条新的命令 则预备好的命令将被取消 而解码新的命令 除非是 W O T F命令 有三条命令可用 如表1所示 SRST 系统复位 格式 从主机到到目标 参数 无 SRST 命令仅仅在SW I M CSR的SW I