电子技术课程设计指导书程序.doc

电子技术课程设计指导书程序附表第二部分 基本性实验实验1基本逻辑门电路的VHDL设计设计程序1. 2 输入与非门的 VHDL 描述LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2_lab1 IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END nand2_lab1; ARCHITECTURE one OF nand2_lab1 IS BEGIN y= a nand b;END one;2. 2输入或门的 VHDL 描述LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2_lab IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END or2_lab; ARCHITECTURE one OF or2_lab IS BEGIN y= a or b;END one; 3. 非门的 VHDL 描述LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY hnot IS PORT(a : IN STD_LOGIC; y: OUT STD_LOGIC); END hnot; ARCHITECTURE one OF hnot IS BEGIN y= not a;END one; 4. 异或门的 VHDL 描述LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY xor2_lab IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END xor2_lab; ARCHITECTURE one OF xor2_lab IS BEGIN y= a xor b;END one;实验2组合逻辑电路的VHDL设计设计程序1. 8-3编码器的 VHDL 描述LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY encoder83 IS PORT( d : IN STD_LOGIC_VECTOR(7 DOWNTO 0); encode: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END encoder83;ARCHITECTURE one OF encoder83 ISBEGINencode = 111 when d(7) = 1 else 110 when d(6) = 1 else 101 when d(5) = 1 else 100 when d(4) = 1 else 011 when d(3) = 1 else 010 when d(2) = 1 else 001 when d(1) = 1 else 000 when d(0) = 1 ;END one;2. 3线-8线通用译码器的 VHDL 描述LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY decoder IS PORT(a,b,c : IN STD_LOGIC; G1,G2a,G2b : IN STD_LOGIC; Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); END decoder;ARCHITECTURE decoder_arc OF decoder IS SIGNAL indata : STD_LOGIC_VECTOR (2 DOWNTO 0); BEGIN indata Y Y Y Y Y Y Y Y Y = NULL; END CASE; ELSE Y = 11111111 ; END IF; END PROCESS; END decoder_arc;3. 7段数码显示译码器的 VHDL 描述LIBRARY IEEE;USE ieee.std_logic_1164.all;ENTITY leddecoder ISPORT (a3,a2,a1,a0 :in std_logic; Ya,Yb,Yc,Yd,Ye,Yf,Yg:out std_logic);END leddecoder;ARCHITECTURE led_arc of leddecoder ISsignal A: std_logic_vector(3 downto 0);signal Y: std_logic_vector(6 downto 0);BEGIN A= a3 & a2 & a1 & a0 ;Ya = Y(6);Yb = Y(5);Yc = Y(4);Yd = Y(3);Ye = Y(2);Yf = Y(1);Yg = Y(0);With A selectY z z z zz= X; END CASE;END PROCESS; END one;实验3时序逻辑电路的VHDL设计设计程序1触发器的VHDL描述LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dff_logic IS PORT( d,clk: IN STD_LOGIC; q : OUT STD_LOGIC); END dff_logic;ARCHITECTURE dff1 OF dff_logic ISBEGIN PROCESS(clk) BEGIN IF clkEVENT AND clk=1 THEN q=d; END IF; END PROCESS; END dff1; 24位二进制加法计数器的VHDL描述LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt4 IS PORT(CLK: IN STD_LOGIC; Q :buffer STD_LOGIC_VECTOR(3 DOWNTO 0); END cnt4;ARCHITECTURE bhv OF cnt4 ISBEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN Q = Q + 1; END IF; END PROCESS; END bhv; 3十进制计数器的VHDL描述LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count10 isPORT (cp : INSTD_LOGIC; q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END count10;ARCHITECTURE one OF count10 IS SIGNAL count :STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN PROCESS (cp) BEGIN IF cpEVENT AND cp=1 THEN IF count =1001 THEN count =0000; ELSE count = count +1; END IF; END IF; END PROCESS; q= count;END one;44位基本寄存器的VHDL描述LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY registerb isPORT (cp,reset : INSTD_LOGIC; data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END registerb;ARCHITECTURE one OF registerb IS BEGIN PROCESS (cp)BEGIN IF cpEVENT AND cp=1 THEN IF reset=1 THEN q=0000; ELSE q= data; END IF; END IF; END PROCESS;END one;实验4 QuartusII的原理图设计和层次化设计设计程序1. 1位全加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity full_adder is port (a, b, c: in std_logic; carry, sum: out std_logic); end full_adder;architecture a of full_adder isbegin sum=a xor b xor c; carry=(a and b) or (a and c) or (b and c); end a;2. 由全加器完成4位加法器的设计library ieee; -四位加法器use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity b4_adder isport (a, b: in std_logic_vector (3 downto 0); s : out std_logic_vector (4 downto 0); end b4_adder;architecture a of b4_adder is signal c: std_logic_vector (4 downto 0);component full_Adder-元件说明语句，形成底层元件 port ( a, b, c : in std_logic; carry, sum: out std_logic);end component;beginu0: full_adder port map (a (0), b (0), c (0), c (1), s (0);-元件例化语句，调用底层元件u1: full_adder port map (a (1), b (1), c (1), c (2), s (1);-采用位置映射，建立调用关联关系u2: full_adder port map (a (2), b (2), c (2), c (3), s (2);u3: full_adder port map (a (3), b (3), c (3), c (4), s (3);c(0) = 0; s(4)=c(4);End a;实验5 算术运算电路的VHDL设计设计程序1.实现4位二进制数a、b的加法、减法和乘法运算的VHDL程序设计。library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity arithmetic isport (a,b: in std_logic_vector (3 downto 0);-定义两个输入4位二进制数a和b q1 : out std_logic_vector (4 downto 0);-定义加法运算和的输出q1 q2 : out std_logic_vector (3 downto 0);-定义减法运算差的输出q2 q3 : out std_logic_vector (7 downto 0);-定义乘法运算积的输出q3end arithmetic;architecture behave of arithmetic isbeginq1= ( 0&a)+( 0 &b); -实现二进制数的加法运算q2=a-b; -实现二进制数的减法运算q3=a*b; -实现二进制数的乘法运算end behave;2. 实现两个8位二进制数是否相等的比较，输入数据分别是a和b，输出为y，当a=b时，y=1，否则y=0。library ieee;use ieee.std_logic_1164.all;entity compare is port (a,b: in std_logic_vector (7 downto 0);-定义两个输入8位二进制数据a和by: out std_logic);-定义比较输出yend compare;architecture behave of compare is beginprocess (a,b)beginif (a=b) then y=1;-两个数据相等，则输出y=1else y=0;-两个数据不等，则输出y=0end if;end process;end behave;3. 求补器的输入为a(7)a(0)，输出为b(7)b(0)，设a(7)和b(7)为符号位。输入a(7) = 0，表明a是正数时，输出正数的补码b等于原码a；当输入a(7) = 1，表明a是负数，输出负数的补码b等于原码求反加1。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity complement is port (a: in