锁相环原理以及倍频分频实现.doc

锁相环原理以及倍频/分频实现Aphase-locked loop(PLL) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. Figure 1 shows a simplified block diagram of the major components in a PLL. The main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters(C).注.锁相环是一种基于输入信号与输入信号反馈给振荡控制器的信号之间的相位差的闭环频率控制系统.图1 展示了锁相环的基本原理框图。图中的PLL主要由鉴相器（PFD），电荷泵，回路滤波器，压控振荡电路（VCO）,计数器（反馈技术器M，预分频技术器N，后分频C）.Figure 1. Block Diagram of a PLLPLLs in AlteraFPGAs align the rising edge of the reference input clock to a feedback clock using the PFD. The falling edges are determined by the duty-cycle specified by the user. The PFD detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO needs to operate at a higher or lower frequency, respectively.注.Altera FPFG 芯片内的PLL中,在每个参考时钟的上升沿将通过鉴相器(PFD) 产生一个反馈时钟信号.由用户指定的占空比来决定时钟的下降沿.PFD检测参考时钟与反馈时钟之间的频率差以及相位差并产生”up”或”down”的控制信号.这个控制信号表征着反馈信号是超前还是落后于参考时钟信号.这两种不同的信号决定着压控振荡器(VCO)是否需要提高频率或者降低频率.The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter.注.PFD产生的”up”,down”将输出给电荷泵,如果电荷泵接收到的是”up”信号,电流将进入环路滤波.相反的将从环路滤波器中吸取电流.The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.注.环路滤波将”up”down”信号准换为压控信号传递给压控振荡器.并控制压控振荡器的振荡频率.如果PFD产生的是”up”信号,VCO将提高振荡频率,相反减少振荡频率.直到参考时钟信号与反馈时钟信号具有相同的振荡频率以及相位. 环路滤波器将滤除电荷泵产生的噪声振荡并且防止电压过载.When the reference clock and the feedback clock are aligned, the PLL is considered locked. To find reasons why a PLL may lose lock, seeWhy Does My PLL Lose Lock?注.当参考频率与反馈频率一致的时候,PLL被称为锁定.A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREFthat is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.注.反馈回路上插入一个除法器(M)可以在参考时钟频率的基础上实现M倍频.PFD的输入频率等于输入频率/N.The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).In the form of equations: FREF= FIN/ N FVCO= FREF M = FIN M/N FOUT= FVCO/ C = (FREF M) / C = (FIN M) / (N C)where: FVCO= VCO frequency FIN= input frequency FREF= reference fr