数字逻辑电路大型实验-4位数字频率计.doc

4位数字频率计一、实验內容用PLD设计一4位数字频率计，测量范围为09999Hz，设被测信号为方波，幅值已满足要求。二、数字频率计的设计1工作原理：数字频率计的原理框图如下图所示。当闸门信号（宽度为1S的正脉冲）到来时，闸门开通，被测信号通过闸门送到计数器，计数器开始计数，当闸门信号结束时，计数器停止计数。由于闸门开通时间为1S，计数器的计数值就是被测信号频率。为了使测得的频率值准确，在闸门开通之前，计数器必须清零。为了使显示电路稳定地显示频率值，在计数器和显示电路之间加了锁存器，当计数器计数结束时，将计数值通过锁存信号送到锁存器。控制电路在时基电路的控制下产生三个信号：闸门信号、锁存信号和清零信号。2数字频率计原理图：（上图：原理框图；下图：原理图）3CNT10、CNT12、CODE、LOCK模块的VHDL语言程序；CNT10SRClibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport(clk: in std_logic;clr: in std_logic;cs: in std_logic;qq: buffer std_logic_vector(3 downto 0);co: out std_logic);end cnt10;architecture one of cnt10 isbeginprocess(clk, clr, cs)beginif (clr = 1) then qq = 0000;elsif (clkevent and clk = 1) thenif (cs = 1) thenif (qq = 9) thenqq = 0000;elseqq = qq + 1;end if;end if;end if;end process;process(qq)beginif (qq = 9) thenco = 0;elseco = 1;end if;end process;end one;CNT12SRClibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt12 isport(clk: in std_logic;qq: buffer std_logic_vector(3 downto 0);end cnt12;architecture one of cnt12 isbeginprocess(clk)beginif (clkevent and clk=1) thenif (qq = 11) thenqq = 0000;elseqq = qq + 1;end if;end if;end process;end one;CODE SRClibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity code isport(dd: in std_logic_vector(3 downto 0);cs: out std_logic;clr: out std_logic;lock: out std_logic);end code;architecture one of code isbeginprocess(dd)beginif (dd = 0) thenclr = 1;elseclr = 0;end if;if (dd = 11) thenlock = 1;elselock 0) and (dd 9) thencs = 1;elsecs = 0;end if;end process;end one;LOCK SRC library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity lock isport(clk: in std_logic;dd: in std_logic_vector(3 downto 0);qq: out std_logic_vector(3 downto 0);end lock;architecture one of lock isbeginprocess(clk, dd)beginif (clkevent and clk = 1) thenqq IF(start=1)THEN next_state=S1; ELSE next_statenext_statenext_stateIF(i4=1)THEN next_state=s0; ELSE next_stateendd=1;clr=1;ca=0;cb1=0;cb0=0; cm1=0;cm0=0;ccendd=0;clr=0;ca=1;cb1=1;cb0=1; cm1=0;cm0=0;ccIF(bi=1)THEN endd=0; clr=1;ca=0;cb1=0;cb0=0; cm1=1;cm0=1;cc=1; ELSE endd=0; clr=1;ca=0;cb1=0;cb0=0; cm1=0;cm0=0;ccendd=0;clr=1;ca=0;cb1=0;cb0=1; cm1=0;cm0=1;cc=0; END CASE;END PROCESS com2;reg:PROCESS(clk) BEGIN IF clk=1 AND clkEVENT THEN