可编程逻辑 音乐曲谱演奏.doc

实验三 乐曲演奏电路设计一实验目的和要求1、熟悉状态机编写的基本原理2、掌握状态图的画法3、掌握mooer类型和mealy类型的状态机的代码编写4、掌握音乐发生的原理与电路的实现二实验内容1、了解乐曲产生的原理：采用FPGA器件驱动小扬声器构成一个乐曲演奏电路。乐曲能够演奏有两个基本数据：音调驱动信号的频率和音长驱动信号持续的时间。只要控制输出到扬声器的激励信号频率的高低和持续的时间，就可以使扬声器发出连续的乐曲声。音乐的十二平均率规定：每两个8度音（如简谱中的中音1和高音1）之间的频率相差1倍；每两个8度音之间又可分为12个半音，每两个半音的频率比为1/12；音名A（简谱中的低音6）的频率为440Hz。根据该原理计算每个音符的频率：2、根据乐曲演奏的原理，对乐曲演奏电路进行模块划分：3、使用Verilog HDL编写乐曲演奏电路，实现回梦游仙片段的演奏。三主要实验仪器与器材1、计算机2、FPGA实验开发板程序代码：四实验结果程序代码：module top(clk,rst,en,speaker,sel,disout);input clk,rst,en;output speaker;output 3:0sel;output 6:0disout;wire 3:0 count1,count2,count3,count4;wire 3:0 count11,count13,count12;display m1(clk,count1,count2,count3,count4,sel,disout);music m2(clk,rst,speaker1,count11,count12,count13);always (posedge clk) begin if(en)beginspeaker=speaker1;count1=count11;count2=count12;count3=count13;end endendmodule音乐的产生：module music(clk,rst,speaker,high,med,low);input clk,rst;output speaker;output3:0 high,med,low;reg 3:0 high,med,low;reg speaker;reg19:0 dive,divicount;reg6:0 counter;reg newclk;reg22:0 clkcount;/generate speakeralways (posedge clk) begin if(!rst) begin divicount=0;speaker=0; end else begin divicount=divicount+1; if(divicount=dive) begin speaker=speaker;divicount=0; endend end/generate newclkalways (posedge clk) /分频 begin if(!rst) begin clkcount=0;newclk=0; end else begin clkcount=clkcount+1; if(clkcount=6250000) begin newclk=newclk;clkcount=0; end /分频后时钟周期为0.25秒 end endalways (posedge newclk) begin case(high,med,low) /音阶在FPGA中的频率值=50000000/频率值/2 b0000_0101_0000: dive=31888; b0000_0100_0000: dive=31888; b0000_0110_0000: dive=28409; b0000_0111_0000: dive=25303; b0001_0000_0000: dive=23889; b0010_0000_0000: dive=21276; b0011_0000_0000: dive=18968; b0000_0000_0000: dive=100000; endcase endalways (posedge newclk) begin if(!rst) counter=0; else begin counter=counter+1; case(counter) /曲谱 0: high,med,low=b0011_0000_0000; 1: high,med,low=b0011_0000_0000; 2: high,med,low=b0010_0000_0000; 3: high,med,low=b0010_0000_0000; 4: high,med,low=b0011_0000_0000; 5: high,med,low=b0011_0000_0000; 6: high,med,low=b0011_0000_0000; 7: high,med,low=b0011_0000_0000; 8: high,med,low=b0011_0000_0000; 9: high,med,low=b0011_0000_0000; 10: high,med,low=b0000_0110_0000; 11: high,med,low=b0000_0110_0000; 12: high,med,low=b0010_0000_0000; 13: high,med,low=b0010_0000_0000; 14: high,med,low=b0010_0000_0000; 15: high,med,low=b0010_0000_0000; 16: high,med,low=b0001_0000_0000; 17: high,med,low=b0001_0000_0000; 18: high,med,low=b0000_0111_0000; 19: high,med,low=b0000_0111_0000; 20: high,med,low=b0000_0110_0000; 21: high,med,low=b0000_0110_0000; 22: high,med,low=b0000_0110_0000; 23: high,med,low=b0000_0111_0000; 24: high,med,low=b0000_0110_0000; 25: high,med,low=b0000_0110_0000; 26: high,med,low=b0000_0101_0000; 27: high,med,low=b0000_0101_0000; 28: counter=0 endcase end endendmodule显示程序：module display(clk,count1,count2,count3,count4,sel,disout);input clk;input 3:0count1; input 3:0count2;input 3:0count3;input 3:0count4;output 3:0 sel;output 6:0 disout;reg 3:0 sel;reg 6:0 disout;reg 17:0 temp;reg 1:0 selcount;reg 3:0 count;/*always (posedge clk) begin selcount=selcount+1; end*/always (posedge clk) begin temp=temp+1; if(temp=150000) begin selcount=selcount+1;temp=0; end case(selcount) 0: begin count=count1;sel=4b1110; end1: begin count=count2;sel=4b1101; end2: begin count=count3;sel=4b1011; end3: begin count=count4;sel=4b0111; end endcase endalways (posedge clk) begin case(count) 0: disout=7b1111110;1: disout=7b0110000;2: disout=7b1101101;3: disout=7b1111001;4: disout=7b011001