Verilog HDL 8位计数器counter的程序注释.doc

一、8位计数器counter.v的源程序module counter (count, clk, rst);output 7:0 count;input clk, rst;reg 7:0 count;parameter tpd_clk_to_count = 1;parameter tpd_reset_to_count = 1;function 7:0 increment; input 7:0 val;reg 3:0 i;reg carry; begin increment = val; carry = 1b1; /* * Exit this loop when carry = zero, OR all bits processed */ for (i = 4b0; (carry = 4b1) | (i = 7); i = i+ 4b1) begin incrementi = vali carry; carry = vali & carry; end end endfunction/* * The following always block was changed to make it synthesizable.always (posedge clk or posedge rst) if (rst) count = #tpd_reset_to_count 8h00; else count = #tpd_clk_to_count increment(count);*/always (posedge clk or posedge rst) if (rst) count = 8h00; else count = count + 8h01; endmodule二、8位计数器counter.v的测试文件tcounter.vmodule test_counter;reg clk, rst;wire 7:0 count;counter #(5,10) dut (count,clk,rst); /dutmodule instance/* 这里#(5,10)表示分别改变被引用模块counter中的参数tpd_clk_to_count和tpd_reset_to_count为5和10 ，参见数字系统设计与Verilog HDLP174例6.16 */initial / Clock generator begin clk = 0; #10 forever #10 clk = !clk; / clk的时钟周期为20 end initial/ Test stimulus begin rst = 0; #5 rst = 1; #4 rst = 0; /rst maintains high level for only 4 time units. #50000 $stop; /经过50000个时间单位，则暂停仿真。这里$stop为系统任务 end initial$monitor($stime, rst, clk, count); /* $monitor为系统任务，监控和输出参数列表中的表达式或变量值，并在Main窗口中显示（见下图）。这里$stime为系统函数，返回仿真的当前时间值，为一个截去高位保留低32位的无符号整数 */ endmodule注：在$monitor($stime, rst, clk, coun