TLM设计实例.doc

TLM设计实例简易DMA设计在一个SoC芯片中，一般由处理器、DMA控制器、中断控制器、存储器、各种接口如UART、USB等组成。DMA往往是总线的主设备，它可以发起存储器之间的数据传输。同时DMA也是总线的从设备，DMA中有若干个控制寄存器，当配置这些寄存器的时候DMA作为总线的从设备。因此DMA（和总线之间有两种接口，一种是主设备接口master_if，另一种则是从设备接口slave_if。作为TLM设计实例的简易DMA（以下简称DMA）中有五个寄存器。DMA使能寄存器用来使能DMA模块，burst传输长度控制器控制每个burst传输的长度，传输控制器控制总的传输长度。源地址寄存器和目的地址寄存器中分别设置数据传输的源地址和目的地址。在DMA中以burst的方式先从源地址读取数据并缓存到DMA内部的buffer中，然后将数据写到目的地址中去。在下面的内容中将给出两种DMA事务级建模的方法。在第一种模型中没有时钟，而第二种模型是周期精确的。在这两种事务级模型中，都有三种端口分别是初始化端口、总线主设备接口和总线从设备接口。在没有时钟的事务级模型中有三个进程分别是main_action进程、dma_fsm进程和dma_rst进程。其中main_action进程和dma_fsm进程定义为SC_THREAD类型，在SC_THREAD进程没有时钟。由于进程间的通信需要通过通道，因此定义了两个信号用于进行间的通信，信号是通道的一种。DMA.h文件如下：#ifndef _dma_h#define _dma_h#include #include slave_if.h#include master_if.henum state_typeidle,read_state,write_state;SC_MODULE(dma)public: /portssc_in rst; /初始化信号 sc_port master_port; /总线主设备接口 sc_port slave_port; / 总线从设备接口 /signalsc_signal my_state; /用来做进程间通信sc_signal dma_enable; /用来做进程间通信SC_HAS_PROCESS(dma); /macro definition/DMA构造函数dma(sc_module_name name_, unsigned int start_address, unsigned int end_address): sc_module(name_),reg_start_address(start_address),reg_end_address(end_address) / process declarationSC_THREAD(main_action); sensitive my_state;SC_THREAD(dma_fsm);sensitive my_state dma_enable;SC_METHOD(dma_rst);sensitive_neg rst; / process void main_action(); void dma_fsm(); void dma_rst(); /slave interface bool slave_read(int *data, unsigned int address)； bool slave_write(int *data, unsigned int address)； bool slave_select(unsigned address)； private: unsigned int dma_en; /dma_en寄存器; unsigned int transfer_size; /transfer size寄存器; unsigned int burst_length; /burst length寄存器; unsigned int source_address; /source address寄存器; unsigned int destin_address; /destination address寄存器;state_type state; /DMA状态：初始化状态、读状态、写状态 int dma_buffer16; /DMA 缓存 int * buffer; /DMA 缓存指针 unsigned int reg_start_address; /DMA寄存器地址空间首地址 unsigned int reg_end_address; /DMA寄存器地址空间末地址; #endifDMA总线主设备接口中定义了两个读写函数master_read和master_write。Master_if.h文件如下：ifndef _master_if_h#define _master_if_h#include class master_if : public virtual sc_interfacepublic: / master interface virtual bool master_read(int *data , unsigned int address ) = 0; virtual bool master_write(int *data , unsigned int address) = 0; ; / end class master_if#endifDMA总线从设备接口除了定义读写函数外，还定义了一个slave_select函数。该函数用来当从设备被选中时对总线的一个回应。Slave_if.h文件如下：#ifndef _slave_if_h#define _slave_if_h#include class slave_if : public virtual sc_interfacepublic: / Slave interface virtual bool slave_read(int *data, unsigned int address) = 0; virtual bool slave_write(int *data, unsigned int address) = 0; virtual bool slave_select(unsigned int address)=0; / end class slave_if#endif 在dma.cpp文件中实现了从设备接口中定义的方法和dma的进程方法。#include dma.hvoid dma:main_action() /dma数据读写函数 unsigned int read_cnt=burst_length; unsigned int write_cnt=burst_length; while(dma_en & (rst) wait(); if(state=idle) buffer=dma_buffer; if (state=read_state) /read the data from slave_a while(read_cnt) master_port-master_read(buffer, source_address); read_cnt-; source_address+; buffer+; read_cnt=burst_length; if (state=write_state) /write the data to slave_b while(write_cnt) master_port-master_write(buffer, destin_address); write_cnt-; destin_address+; buffer+; write_cnt=burst_length; void dma:dma_fsm() /dma状态机 dma_enable=dma_en; while(dma_en & (rst) & (transfer_size0) wait();if(state=idle) wait(10,SC_NS);state=read_state;my_state=state;buffer=dma_buffer;if(state=read_state)wait(80,SC_NS);state=write_state;my_state=state;buffer=dma_buffer;if (state=write_state) wait(80,SC_NS);transfer_size=transfer_size-burst_length;state=idle;my_state=state; /end_while/end_dma_fsmvoid dma:dma_rst() /初始化函数state=idle; /状态初始化 dma_en=0; /寄存器清0操作 transfer_size=0; burst_length=0; source_address=0; destin_address=0; bool dma:slave_read(int *data, unsigned int address)/从设备接口的读方法 switch(address) case 4: *data=source_address; /source address寄存器地址为4 break;case 8: *data=destin_address; break;case 12: *data=burst_length; break;case 16:*data=transfer_size; breakcase 20: *data=dma_en; break; return 1;bool dma:slave_write(int *data, unsigned int address) /从设备接口的写方法 switch(address) case 4: source_address=*data; /写寄存器 break;case 8:destin_address=*data; break;case 12: burst_length=*data; break;case 16: transfer_size=*data; break;case 20: dma_en=*data; break; return 1;bool dma:slave_select(unsigned address) /判断DMA是否被选中 if(address=reg_start_address)&(address=reg_end_address) return 1; else return 0;周期精确的DMA模型定义了时钟，所有的进程都是SC_METHOD进程。在SC_METHOD进程之间没有通信机制，都通过时钟作为敏感变量触发。dma.h文件如下：#ifndef _dma_h#define _dma_h#include #include slave_if.h#include master_if.henum state_typeidle,read_state,write_state;SC_MODULE(dma)public: /ports sc_in_clock clk; /输入时钟sc_in rst; /初始化信号 sc_port master_port; /总线主设备接口 sc_port slave_port; / 总线从设备接口 SC_HAS_PROCESS(dma); /macro definition/DMA构造函数dma(sc_module_name name_, unsigned int start_address, unsigned int end_address): sc_module(name_),reg_start_address(start_address),reg_end_address(end_address) / process declarationSC_METHOD(main_action); sensitive_pos clk;SC_METHOD(dma_fsm);sensitive_pos clk;SC_METHOD(dma_rst);sensitive_neg burst_read(buffer, source_address);source_address+;buffer+; if (dma_en & (rst) & (state=write_state) master_port-burst_write(buffer, destin_address);destin_address+;buffer+; void dma:dma_fsm() if(dma_en & (rst) & (transfer_size0) switch(state) case idle:state=read_state;counter=burst_length;buffer=dma_buffer; break; case