vhdl设计实例.ppt

可编程器件及数字系统设计 张林行 第五讲 可编程器件及数字系统设计 VHDL设计实例 常用组合逻辑电路设计常用时序逻辑电路设计VHDL程序设计规范 第五讲 VHDL设计实例 1 编码器 2 译码器 3 比较器 4 数据选择器 5 三态输出电路 一 常用组合逻辑电路设计 1 编码器 libraryieee useieee std logic 1164 all entitybmqisport A instd logic vector 7downto0 En in std logic Y outstd logic vector 2downto0 endbmq architecturem1ofbmqissignalsel std logic vector 8downto0 beginsel En architecturem1ofbmqissignalsel std logic vector 8downto0 beginProcess En A BeginIfEn 1 thenifA 00000001 thenY 000 elsifA 00000010 thenY 001 elsifA 00000100 thenY 010 elsifA 00001000 thenY 011 elsifA 00010000 thenY 100 elsifA 00100000 thenY 101 elsifA 01000000 thenY 110 elseY 111 endif ElseY 000 endif endprocess endm1 2 译码器 A 3 8译码器 libraryieee useieee std logic 1164 all entityymqisport Y instd logic vector 2downto0 EN instd logic A outstd logic vector 7downto0 endymq architecturem1ofymqissignalsel std logic vector 3downto0 beginsel En B 码制转换 2 译码器 四位二进制码转换为BCD码 并译码显示 数码管为共阴极 Libraryieee Useieee std logic 1164 all Useieee std logic unsigned all EntitybcdisPort A instd logic vector 3downto0 bcd0 bcd1 outstd logic vector 3downto0 seven0 seven1 outstd logic vector 6downto0 Endbcd Architectureaofbcdissignaltmp std logic vector 3downto0 Beginbcd0 Awhen A 10 elseA 6 bcd1 0000 when A 10 else 0001 tmp bcd0 seven0 0111111 whentmp 0000 else 0 0000110 whentmp 0001 else 1 1011011 whentmp 0010 else 2 1001111 whentmp 0011 else 3 1100110 whentmp 0100 else 4 1101101 whentmp 0101 else 5 1111101 whentmp 0110 else 6 0000111 whentmp 0111 else 7 1111111 whentmp 1000 else 8 1101111 whentmp 1001 else 9 0000000 seven1 0111111 when A 10 else 0000110 Enda 3 比较器 如果a b 输出为 agtb 1 altb 0 aeqb 0 如果a b 输出为 altb 1 agtb 0 aeqb 0 如果a b 输出为 aeqb 1 agtb 0 altb 0 Libraryieee Useieee std logic 1164 all Useieee std logic unsigned all ENTITYcmpabISPORT A B instd logic vector 7downto0 AGTB ALTB AEQB outstd logic ENDcmpab ARCHITECTUREaOFcmpabISBEGINaeqbbelse 0 altb 1 whena belse 0 ENDa ARCHITECTUREbOFcmpabISBEGINprocess a b beginifA Bthenagtb 1 elsifA Bthenaeqb 1 elsealtb 1 endif endprocess ENDb 4 数据选择器 4选1MUX libraryieee useieee std logic 1164 all entitymux41isport A B C D instd logic sel instd logic vector 1downto0 dout outstd logic endmux41 architecturearchmuxofmux41isbeginwithselselectdout Awhen 00 Bwhen 01 Cwhen 10 Dwhenothers endarchmux 5 三态输出电路 EN 1B A EN 0B 高阻态 libraryieee useieee std logic 1164 all entitytrioutisport data in instd logic en instd logic data out outstd logic endtriout architecturebehaveoftrioutisbegindata out data inwhenen 1 else Z endbehave 注意此处的 Z 要大写 libraryieee useieee std logic 1164 all entitytrioutisport data in instd logic vector 7downto0 en instd logic data out outstd logic vector 7downto0 endtriout architecturebehaveoftrioutisbegindata out Z endbehave 注意此处的 Z 要大写 二 常用时序逻辑电路设计 1 D触发器设计 2 移位寄存器设计 3 计数器设计 4 分频器设计 5 状态机设计 序列检测器 1 触发器设计 DQCP D触发器 LIBRARYIEEE USEIEEE STD LOGIC 1164 ALL ENTITYdffISPORT cp d INSTD LOGIC q OUTSTD LOGIC ENDdff ARCHITECTUREaOFdffISBEGINprocess cp beginifcp eventandcp 1 thenq d endif endprocess ENDa 1 触发器设计 RS触发器 LIBRARYieee USEieee std logic 1164 ALL ENTITYffrsISPORT s r INSTD LOGIC q nq OUTSTD LOGIC ENDffrs ARCHITECTUREaOFffrsISsignalqn nqn std logic BEGINqn rnornqn nqn snorqn q qn nq nqn ENDa 2 移位寄存器设计 4位串行输入并行输出右移移位寄存器 libraryieee useieee std logic 1164 all ENTITYshifterISPORT din instd logic reset clk instd logic dout bufferstd logic vector 3downto0 ENDshifter ARCHITECTUREbehaveOFshifter1ISBEGINProcess clk Beginif reset 1 thendout 0 elseif clk Eventandclk 1 thendout dout 2downto0 3 计数器设计 计数器 CLK Q LIBRARYieee USEieee std logic 1164 ALL USEieee std logic unsigned ALL USEieee std logic arith ALL ENTITYcounterISPORT clk inSTD LOGIC q bufferSTD LOGIC vector 3downto0 ENDcounter ARCHITECTUREaOFcounterISBEGINprocess clk beginif clk eventandclk 1 thenq q 1 endif endprocess ENDa ARCHITECTUREaOFcounterISBEGINprocess clk beginif clk eventandclk 1 thenif q 0 endif endprocess ENDa 减法 计数器 CLK Q CLR 3 计数器设计 LIBRARYieee USEieee std logic 1164 ALL USEieee std logic unsigned ALL USEieee std logic arith ALL ENTITYcounterISPORT clk clr inSTD LOGIC q bufferSTD LOGIC vector 3downto0 ENDcounter ARCHITECTUREaOFcounterISBEGINprocess clk beginif clk eventandclk 1 thenif clr 1 thenq 0 elseq q 1 endif endif endprocess ENDa ARCHITECTUREaOFcounterISBEGINprocess clk clr beginif clr 1 thenq 0000 elseif clk eventandclk 1 thenq q 1 endif endif endprocess ENDa 计数器 CLK Q LD DI 3 计数器设计 LIBRARYieee USEieee std logic 1164 ALL USEieee std logic unsigned ALL USEieee std logic arith ALL ENTITYcounterISPORT clk ld instd logic di instd logic vector 3downto0 q bufferstd logic vector 3downto0 ENDcounter ARCHITECTUREaOFcounterISBEGINprocess clk beginif clk eventandclk 1 thenif ld 1 thenq di elseq q 1 endif endif endprocess ENDa ARCHITECTUREaOFcounterISBEGINprocess clk clr beginif ld 1 thenq di elseif clk eventandclk 1 thenq q 1 endif endif endprocess ENDa 4 分频器设计 计数器就是对时钟脉冲计数 同时计数器还是一个分频器 5 状态机设计 我们可以用输入信号X和电路状态Q来描述时序电路的逻辑功能 这时时序电路称为状态机 StateMachine 根据输出信号和输入信号以及电路状态的关系 状态机可以分为两种 穆尔 Moore 型和米利 Mealy 型 Y F X Q Y F Q 米利 Mealy 型 穆尔 Moore 型 输出信号和输入信号无关 输入信号影响状态的转换 1 More型状态机 LIBRARYieee USEieee std logic 1164 ALL ENTITYmoreISPORT Clk reset inStd logic din inStd logic op outStd logic ENDmore ARCHITECTUREaOFmoreISTYPESTATE TYPEIS s0 s1 s2 s3 SIGNALstate STATE TYPE BEGIN PROCESS clk reset BEGINIf reset 1 THENstate s0 elseIF clk EventANDclk 1 THEN CASEstateISWHENs0 IF din 1 THENstateIF din 0 THENstateIF din 0 THENstateIF din 1 THENstate s0 elsestate s1 ENDIF EndCase Endif Endif Endprocess op 1 when state s1 else 0 ENDa S0 S2 0 0 1 0 S3 1 1 S1 1 1 0 0 0 0 0 0 1 1 2 Mealy型状态机 LIBRARYieee USEieee std logic 1164 ALL ENTITYmealyISPORT Clk reset INSTD LOGIC clockdin INSTD LOGIC op OUTSTD LOGIC ENDmealy ARCHITECTUREaOFmealyISTYPESTATE TYPEIS s0 s1 s2 s3 SIGNALstate STATE TYPE BEGIN PROCESS clk reset BEGINIf reset 1 THENstate s0 elseIf clk EVENTANDclk 1 then CASEstateISWHENs0 IFdin 1 THENstateIFdin 0 THENstateIFdin 0 THENstateIFdin 1 THENstate s0 elsestate s1 ENDIF ENDCASE Endif Endif ENDPROCESS