Verilog程序9、SRAM读写实验.docx

SRAM采用IS62LV256-70U，其部分引脚为：（具体情况参考相应的datasheet） 读时序：WE持续为高，CE和OE一直为低。写时序：timescale 1ns / 1ps/ Company:/ Engineer:/ Create Date: 20:44:47 11/17/2010/ Design Name:/ Module Name: sram/ Project Name:/ Target Devices:/ Tool versions:/ Description:/ Dependencies:/ Revision:/ Revision 0.01 - File Created/ Additional Comments:/module sram(clk,rst_n,led,sram_addr,sram_wr_n,sram_data);input clk,rst_n;output led;/sram的引脚output 14:0 sram_addr;output sram_wr_n;inout 7:0 sram_data;/中间变量的定义reg 7:0 wr_data; /写入的数据reg 7:0 rd_data; /读取的数据reg 14:0 addr_r;wire sram_wr_reg,sram_rd_reg;reg led_r;/延时计数器reg 25:0 delay;always (posedge clk or negedge rst_n)if(!rst_n)delay = 26d0;elsedelay = delay +1b1;assign sram_wr_reg = (delay = 26d9999);assign sram_rd_reg = (delay = 26d19999);/对sram的所?地址进行读写 地址遍历 仅仅改变地址和数据，并没有进行读写always (posedge clk or negedge rst_n)if(!rst_n)addr_r = 8d0;else if(delay = 26d29999)addr_r = addr_r +1b1;/对sram的所有地址进行读写 写always (posedge clk or negedge rst_n)if(!rst_n)wr_data = 8d0;else if(delay = 26d29999)wr_data = wr_data +1b1;/读写数据比较always (posedge clk or negedge rst_n)if(!rst_n)led_r = 15d0;else if(wr_data = rd_data)led_r = 1b1;elseled_r = 1b0;assign led = led_r; /延时计数器 在读写时，写入地址后腰延迟至少是70ns。define delay_80ns (cnt = 4d7) reg 2:0 cnt;always (posedge clk or negedge rst_n)if(!rst_n)cnt = 8d0;elsecnt = cnt +1b1; /利用两条always语句块来写状态机。reg 3:0 cstate,nstate;parameter IDLE = 4d0,WR1 = 4d1,WR2 = 4d2,RD1 = 4d3,RD2 = 4d4;always (posedge clk or negedge rst_n)if(!rst_n)cstate = IDLE;elsecstate = nstate;always (cstate or sram_wr_reg or sram_rd_reg or cnt)case(cstate)IDLE:if(sram_wr_reg)nstate = WR1;else if(sram_rd_reg)nstate = RD1;elsenstate = IDLE;WR1:if(delay_80ns)nstate = WR2;elsenstate = WR1;WR2:nstate = IDLE;RD1:if(delay_80ns)nstate = RD2;elsenstate = RD1;RD2:nstate = IDLE;default:nstate = IDLE;endcaseassign sram_addr = addr_r;reg sdlink;/读取数据always (posedge clk or negedge rst_n)if(!rst_n)rd_data = 8d0;elserd_data = sram_data;/写入数据 always (posedge clk or negedge rst_n)if(!rst_n)sdlink = 1b0;elsecase(cstate)IDLE:if(sram_wr_reg)sdlink = 1b1;elsesdlink = 1b0; /我省去了else if(sram_rd_reg),不知道可不可以。WR1:sdlink