3-8译码器的VHDL设计.doc

3-8译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER38A IS PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY DECODER38A;ARCHITECTURE ONE OF DECODER38A ISSIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGINS=A2&A1&A0&S1&S2&S3; WITH S SELECT Y=11111110 WHEN 000100, 11111101 WHEN 001100, 11111011 WHEN 010100, 11110111 WHEN 011100, 11101111 WHEN 100100, 11011111 WHEN 101100, 10111111 WHEN 110100, 01111111 WHEN 111100, 11111111 WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形图4.仿真波形分析当S1 S2 S3=100时，只有当A2 A1 A0=111时，Y7才输出低电平，否则为高电平，当A2 A1 A0=110时，Y6才输出低电平，否则为高电平，当A2 A1 A0=101时，Y5才输出低电平，否则为高电平，Y4到Y0同理。可见该程序设计的是3-8译码器三、共阳极数码管七段显示译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DISPLAY_DECODER IS PORT(A3,A2,A1,A0:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY DISPLAY_DECODER;ARCHITECTURE ONE OF DISPLAY_DECODER ISSIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINS=A3&A2&A1&A0; WITH S SELECT Y1001，即大于9，数码管无显示。由此可知，程序设计的是七段显示译码管。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COMPARE4 IS 四位比较器 PORT(IA_MORE_THAN_B:IN STD_LOGIC; 高位比较的标志位的输入 IB_MORE_THAN_A:IN STD_LOGIC; IA_EQUAL_B:IN STD_LOGIC; A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);两个输入 B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); OA_MORE_THAN_B:OUT STD_LOGIC; OB_MORE_THAN_A:OUT STD_LOGIC; OA_EQUAL_B:OUT STD_LOGIC); END COMPARE4;ARCHITECTURE BEHAV OF COMPARE4 ISBEGIN PROCESS(IB_MORE_THAN_A, IA_EQUAL_B,IA_EQUAL_B) BEGIN IF(IA_EQUAL_B=1)THEN从最高位比较，如果高位大则停止比较输出结果，否则进行下一位比较 IF(A(3)B(3)THEN OA_MORE_THAN_B=1;OB_MORE_THAN_A=0;OA_EQUAL_B=0; ELSIF(A(3)B(3)THEN OA_MORE_THAN_B=0;OB_MORE_THAN_A=1;OA_EQUAL_BB(2)THEN OA_MORE_THAN_B=1;OB_MORE_THAN_A=0;OA_EQUAL_B=0; ELSIF(A(2)B(2)THEN OA_MORE_THAN_B=0;OB_MORE_THAN_A=1;OA_EQUAL_BB(1)THEN OA_MORE_THAN_B=1;OB_MORE_THAN_A=0;OA_EQUAL_B=0; ELSIF(A(1)B(1)THEN OA_MORE_THAN_B=0;OB_MORE_THAN_A=1;OA_EQUAL_BB(0)THEN OA_MORE_THAN_B=1;OB_MORE_THAN_A=0;OA_EQUAL_B=0; ELSIF(A(0)B(0)THEN OA_MORE_THAN_B=0;OB_MORE_THAN_A=1;OA_EQUAL_B=0; ELSE 如果输入中两个数相等的标志位为0，则表明高位不相等，停止比较，输出结果。 OA_MORE_THAN_B=0;OB_MORE_THAN_A=0;OA_EQUAL_B=1; END IF; ELSEOA_MORE_THAN_B=IA_MORE_THAN_B;OB_MORE_THAN_A=IB_MORE_THAN_A;OA_EQUAL_B=IA_EQUAL_B; END IF; END PROCESS;END BEHAV;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY comparator IS PORT ( CLK : IN STD_LOGIC; SIN : IN STD_LOGIC_VECTOR (3 DOWNTO 0); SJ : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Q : OUT STD_LOGIC);END comparator;ARCHITECTURE behave OF comparator IS SIGNAL SIN1 : INTEGER RANGE 0 TO 15; SIGNAL SJ1 : INTEGER RANGE 0 TO 15;BEGINSIN1= CONV_INTEGER(SIN);SJ1= C