brief TFT initialize or reinitialize.docx

* brief TFT initialize or reinitialize * Assumes EBI has been configured correctly in BSP_Init(BSP_INIT_DK_EBI) * paramin tftInit Pointer to EBI TFT initialization structure * return true if we should redraw into buffer, false if BC has controlover displaybool TFT_DirectInit(const EBI_TFTInit_TypeDef *tftInit) bool ret; uint32_t i, freq; /* If we are in BC_UIF_AEM_EFM state, we can redraw graphics */ if (BSP_RegisterRead(&BC_REGISTER-UIF_AEM) = BC_UIF_AEM_EFM) /* If were not BC_ARB_CTRL_EBI state, we need to reconfigure display controller */ if (BSP_RegisterRead(&BC_REGISTER-ARB_CTRL) != BC_ARB_CTRL_EBI) | runOnce) /* Enable SSD2119 Serial Port Interface */ BSP_PeripheralAccess(BSP_TFT, true); /* Enable EBI mode of operation on SSD2119 controller */ BSP_DisplayControl(BSP_Display_EBI); BSP_DisplayControl(BSP_Display_ResetAssert); BSP_DisplayControl(BSP_Display_PowerDisable); freq = SystemCoreClockGet(); for (i = 0; i (freq / 100); i+) _NOP(); /* Configure display for Direct Drive Mode Generic + 3-wire SPI mode */ BSP_DisplayControl(BSP_Display_ModeGeneric); BSP_DisplayControl(BSP_Display_PowerEnable); BSP_DisplayControl(BSP_Display_ResetRelease); /* Configure GPIO for EBI and TFT */ TFT_DirectGPIOConfig(); /* Initialize display */ DMD_init(0, (uint32_t) EBI_BankAddress(EBI_BANK2); /* Configure EBI TFT direct drive */ EBI_TFTInit(tftInit); runOnce = false; ret = true; else ret = false; return ret;#define BC_UIF_AEM_EFM (1) /*ARB_CTRL, BC_ARB_CTRL_EBI); break; case BSP_Display_SPI: BSP_RegisterWrite(&BC_REGISTER-ARB_CTRL, BC_ARB_CTRL_SPI); break; case BSP_Display_BC: BSP_RegisterWrite(&BC_REGISTER-ARB_CTRL, BC_ARB_CTRL_BC); break; case BSP_Display_PowerEnable: tmp = BSP_RegisterRead(&BC_REGISTER-DISPLAY_CTRL); tmp |= (BC_DISPLAY_CTRL_POWER_ENABLE); BSP_RegisterWrite(&BC_REGISTER-DISPLAY_CTRL, tmp); break; case BSP_Display_PowerDisable: tmp = BSP_RegisterRead(&BC_REGISTER-DISPLAY_CTRL); tmp &= (BC_DISPLAY_CTRL_POWER_ENABLE); BSP_RegisterWrite(&BC_REGISTER-DISPLAY_CTRL, tmp); break; case BSP_Display_ResetAssert: tmp = BSP_RegisterRead(&BC_REGISTER-DISPLAY_CTRL); tmp |= (BC_DISPLAY_CTRL_RESET); BSP_RegisterWrite(&BC_REGISTER-DISPLAY_CTRL, tmp); break; case BSP_Display_ResetRelease: tmp = BSP_RegisterRead(&BC_REGISTER-DISPLAY_CTRL); tmp &= (BC_DISPLAY_CTRL_RESET); BSP_RegisterWrite(&BC_REGISTER-DISPLAY_CTRL, tmp); break; case BSP_Display_Mode8080: tmp = BSP_RegisterRead(&BC_REGISTER-DISPLAY_CTRL); tmp &= (BC_DISPLAY_CTRL_MODE_GENERIC); BSP_RegisterWrite(&BC_REGISTER-DISPLAY_CTRL, tmp); break; case BSP_Display_ModeGeneric: tmp = BSP_RegisterRead(&BC_REGISTER-DISPLAY_CTRL); tmp |= (BC_DISPLAY_CTRL_MODE_GENERIC); BSP_RegisterWrite(&BC_REGISTER-DISPLAY_CTRL, tmp); break; default: /* Unknown command */ while (1); return BSP_STATUS_OK;* brief Initializes the LCD display* param cmdRegAddr* If set to 0, initialize SSD2119 for direct drive, if set to 1 update* frame buffer base pointer (offset to EBI bank) only* param dataRegAddr* Address in memory for frame buffer base pointer* return* DMD_OK on success, otherwise error codeEMSTATUS DMD_init(uint32_t cmdRegAddr, uint32_t dataRegAddr) uint16_t data; volatile uint32_t i; (void) cmdRegAddr; (void) dataRegAddr; /* Use data reg addr as pointer to frame buffer */ frameBuffer = (uint16_t *) dataRegAddr; if(cmdRegAddr=1) return DMD_OK; SPI_TFT_Init(); DMDIF_writeReg(DMD_SSD2119_VCOM_OTP_1, 0x0006); /* Oscillation driven DCLK */#if 0 data = DMD_SSD2119_OSCILLATION_START_OSCEN; DMDIF_writeReg(DMD_SSD2119_OSCILLATION_START, data);#endif /* Display control */ data = 0; / data |= DMD_SSD2119_DISPLAY_CONTROL_DTE; data |= DMD_SSD2119_DISPLAY_CONTROL_GON; data |= DMD_SSD2119_DISPLAY_CONTROL_D1; data |= DMD_SSD2119_DISPLAY_CONTROL_D0; DMDIF_writeReg(DMD_SSD2119_DISPLAY_CONTROL, data); /* Exit sleep mode */ data = 0; DMDIF_writeReg(DMD_SSD2119_SLEEP_MODE_1, data); /* Wait */ for (i = 0; i 100000; i+); /* Display control */ DMDIF_writeReg(DMD_SSD2119_DISPLAY_CONTROL, 0x33); /* Entry mode */ data = DMD_SSD2119_ENTRY_MODE_DFM_65K DMD_SSD2119_ENTRY_MODE_DFM_SHIFT; data |= DMD_SSD2119_ENTRY_MODE_WMODE; data |= DMD_SSD2119_ENTRY_MODE_NOSYNC; data |= DMD_SSD2119_ENTRY_MODE_DMODE; data |= DMD_SSD2119_ENTRY_MODE_ID1; data |= DMD_SSD2119_ENTRY_MODE_ID0; DMDIF_writeReg(DMD_SSD2119_ENTRY_MODE, data); / DMDIF_writeReg(DMD_SSD2119_DRIVER_OUTPUT_CONTROL, 0x3aef); /* Generic Interface Control */ / data = DMD_SSD2119_GENERIC_INTERFACE_CONTROL_INVDEN; / DMDIF_writeReg(DMD_SSD2119_GENERIC_INTERFACE_CONTROL, data); /* Driver output control */ data = 0; data |= DMD_SSD2119_DRIVER_OUTPUT_CONTROL_REV; data |= DMD_SSD2119_DRIVER_OUTPUT_CONTROL_GD; / data |= DMD_SSD2119_DRIVER_OUTPUT_CONTROL_TB; / data |= DMD_SSD2119_DRIVER_OUTPUT_CONTROL_SM; / data |= DMD_SSD2119_DRIVER_OUTPUT_CONTROL_RL; data |= (DMD_VERTICAL_SIZE - 1) DMD_SSD2119_DRIVER_OUTPUT_CONTROL_MUX_SHIFT); DMDIF_writeReg(DMD_SSD2119_DRIVER_OUTPUT_CONTROL, data); /* LCD AC control */ data = DMD_SSD2119_LCD_AC_CONTROL_BC; data |= DMD_SSD2119_LCD_AC_CONTROL_EOR; /* data |= DMD_SSD2119_LCD_AC_CONTROL_FLC; */ DMDIF_writeReg(DMD_SSD2119_LCD_AC_CONTROL, data); /* RAM data write */ data = 0xff; DMDIF_writeReg(DMD_SSD2119_ACCESS_DATA, data); /* Mark graphics as initialized */ initialized = 1; return DMD_