AT24C02中英对照.doc

EEPROM Features Write Protect Pin for Hardware Data Protection Utilizes Different Array Protection Compared to the AT24C02/04/08/16 Low-voltage and Standard-voltage Operation2.7(VCC =2.7Vto5.5V)1.8(VCC =1.8Vto5.5V) InternallyOrganized256x8(2K),512x8(4K),1024x8(8K)or2048x8(16K) 2-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate for AT24C02A, 04A and 08A 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V and 5V) Clock Rate for AT24C16A 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes are Allowed Self-timed Write Cycle (10 ms max) High Reliability Endurance: One Million Write Cycles Data Retention: 100 Years Automotive Grade and Extended Temperature Devices Available 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP PackagesDescriptionThe AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C02A/04A/08A/16A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that must be hard wired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four4K devices may be addressed on a single bus system. The A0 pin is a no-connect.WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected toVCC, the write protection feature is enabled and operates as shown in the following table.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a startor stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and fromtheEEPROMin8bitwords.The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.Device AddressingThe 2K, 4K and 8K EEPROM devices all require an 8 bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no-connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no-connect.The 16K EEPROM does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no-connects.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8 bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8 bit data word. Following receipt of the 8 bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, WR to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3).The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.Read OperationsCURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Oncethedeviceaddresswiththeread/writeselectbitsettooneisclockedinand acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When thememory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). EEPROM1、与400KHz I2C 总线兼容2、1.8 到6.0 伏工作电压范围3、低功耗CMOS 技术4、写保护功能当WP 为高电平时进入写保护状态5、页写缓冲器6、自定时擦写周期7、1,000,000 编程/擦除周期8、可保存数据100 年9、8 脚DIP SOIC 或TSSOP 封装10、温度范围商业级工业级和汽车级概述CAT24WC01/02/04/08/16 是一个1K/2K/4K/8K/16K 位串行CMOS E2PROM 内部含有128/256/512/1024/2048 个8 位字节。CATALYST 公司的先进CMOS 技术实质上减少了器件的功耗。CAT24WC01 有一个8 字节页写缓冲器CAT24WC02/04/08/16 有一个16 字节页写缓冲器。该器件通过I2C 总线接口进行操作，有一个专门的写保护功能。管脚描述A0 A1 A2 器件地址选择SDA 串行数据/地址SCL 串行时钟WP 写保护Vcc +1.8V 6.0V 工作电压Vss 地SCL 串行时钟CAT24WC01/02/04/08/16 串行时钟输入管脚用于产生器件所有数据发送或接收的时钟，这是一个输入管脚。SDA 串行数据/地址CAT24WC01/02/04/08/16 双向串行数据/地址管脚用于器件所有数据的发送或接收，SDA 一个开漏输出管脚，可与其它开漏输出或集电极开路输出进行线或wire-OR。A0 A1 A2 器件地址输入端这些输入脚用于多个器件级联时设置器件地址，当这些脚悬空时默认值为0 ，24WC01 除外。当使用24WC01 或24WC02 时最大可级联8 个器件，如果只有一个24WC02 被总线寻址这三个地址输入脚A0 A1 A2 可悬空或连接到Vss， 如果只有一个24WC01 被总线寻址这三个地址输入脚A0 A1 A2 必须连接到Vss。当使用24WC04 时最多可连接4 个器件该器件仅使用A1 A2 地址管脚A0 管脚未用可以连接到Vss 或悬空，如果只有一个24WC04 被总线寻址，A1 和A2 地址管脚可悬空或连接到Vss。当使用24WC08 时最多可连接2 个器件且仅使用地址管脚A2 A0 ，A1 管脚未用可以连接到Vss 或悬空，如果只有一个24WC08 被总线寻址A2 管脚可悬空或连接到Vss。当使用24WC16 时最多只可连接1 个器件所有地址管脚A0 A1 A2 都未用管脚可以连接到Vss 或悬空。WP 写保护如果WP 管脚连接到Vcc，所有的内容都被写保护只能读。当WP 管脚连接到Vss 或悬空，允许器件进行正常的读/写操作。功能描述CAT24WC01/02/04/08/16 支持I2C 总线数据传送协议。I2C 总线协议规定：任何将数据传送到总线的器件作为发送器，任何从总线接收数据的器件为接收器。数据传送是由产生串行时钟和所有起始停止信号的主器件控制的。主器件和从器件都可以作为发送器或接收器，但由主器件控制传送数据（发送或接收）的模式。通过器件地址输入端A0 A1 和A2 可以实现将最多8 个24WC01 和24WC02 器件，4个242C04 器件，2 个24WC08 器件和1 个24WC16 器件连接到总线上。I2C 总线协议I2C 总线协议定义如下（1） 只有在总线空闲时才允许启动数据传送（2） 在数据传送过程中当时钟线为高电平时数据线必须保持稳定状态不允许有跳变，时钟线为高电平时，数据线的任何电平变化将被看作总线的起始或停止信号起始信号时钟线保持高电平期间数据线电平从高到低的跳变作为I2C 总线的起始信号停止信号时钟线保持高电平期间数据线电平从低到高的跳变作为I2C 总线的停止信号器件寻址主器件通过发送一个起始信号启动发送过程，然后发送它所要寻址的从器件的地址。8 位从器件地址的高4 位固定为1010 （见图5） 。接下来的3 位A2 A1 A0 为器件的地址位，用来定义哪个器件以及器件的哪个部分被主器件访问，上述8 个CAT24WC01/02 4 个CAT24WC04 2 个CAT24WC081 个CAT24WC16 可单独被系统寻址。从器件8 位地址的最低位，作为读写控制位。“1” 表示对从器件进行读操作，“0” 表示对从器件进行写操作。在主器件发送起始信号和从器件地址字节后，CAT24WC01/02/04/08/16 监视总线并当其地址与发送的从地址相符时响应一个应答信号（通过SDA 线）CAT24WC01/02/04/08/16 再根据读写控制位（R/W） 的状态进行读或写操作写操作字节写在字节写模式下，主器件发送起始命令和从器件地址信息（R/W 位置零）给从器件，在从器件产生应答信号后，主器件发送CAT24WC01/02/04/08/16 的字节地址，主器件在收到从器件的另一个应答信号后，再发送数据到被寻址的存储单元。CAT24WC01/02/04/08/16 再次应答，并在主器件产生停止信号后开始内部数据的擦写，在内部擦写过程中，CAT24WC01/02/04/08/16 不再应答主器件的任何请求。页写用页写，CAT24WC01 可一次写入8 个字节数据，CAT24WC02/04/08/16 可以一次写入16 个字节的数据。页写操作的启动和字节写一样，不同在于传送了一字节数据后并不产生停止信号。主器件被允许发送P（ CAT24WC01： P=7 ，CAT24WC02/04/08/16： P=15 ）个额外的字节每发送一个字节数据后CAT24WC01/02/04/08/16 产生一个应答位并将字节地址低位加1 ，高位保持不变。如果在发送停止信号之前主器件发送超过P+1个字节，地址计数器将自动翻转，先前写入的数据被覆盖。接收到P+1字节数据和主器件发送的停止信号后，CAT24CXXX启动内部写周期将数据写到数据区。所有接收的数据在一个写周期内写入CAT24W