TVP5150AM1引脚及寄存器说明.doc

TVP5150AM1武秋阳张蒙蒙TVP5150AM1是超低功耗、支持NTSCPALSECAM等格式的高性能视频解码器，在正常工作时，它的功耗仅115mW，并且具有超小封装(32脚的TQFP)，因此非常适用于便携、批量大、高质量和高性能的视频产品。它可以接收2路复合视频信号(CVBS)或1路S-Video信号。通过单片机I2C总线设置内部寄存器，可以输出8位4：2：2的ITU-RBT.656信号(同步信号内嵌)，以及8位4：2：2的ITU-RBT.601信号(同步信号分离，单独引脚输出)。TVP5150AM1信号引脚：TVP5150AM1芯片手册上的引脚的功能介绍：翻译后的引脚说明:标识引脚号功能I/O备注AIP1A、B1、2模拟视频输入，连接到视频模拟输入通过0.1uF到1uF的电容器。最大的输入范围是从0-0.75Vpp,也许还需要一个衰减器来降低输入的振幅到期望的水平。如果不使用的话，通过一个0.1uF的电容器来连接到AGNDIINTREQ/GPCL/VBLK27INTREQ: 中断请求输出GPCL:通用的控制逻辑。这个终端有三个功能:1。通用的输出。在这种模式下的状态GPCL直接通过I2C编程。2。垂直空白输出。在这种模式下使用GPCL终端显示垂直消隐间隔输出的视频。这个信号的开始和结束时间都通过I2C编程。3。同步锁控制输入。在这种模式下,当GPCL是高电平时,输出时钟频率和同步时间被设为额定值。O复用AVID26有效视频指示。这个信号在UV终端和Y终端的水平有效期间的视频输出是高电平。AVID在垂直消隐间隔期间继续切换。这个终端可以放置在一个高阻抗状态。OHSYNC25行同步OVSYNC/PALI24VSYNC: 场同步信号PALI: PAL line indicator or horizontal lock indicatorO复用FID/GLCO23奇偶场标识FID:1代表奇场，0代表偶场 GLCO：这个串行输出携带了彩色pll信息，一个从设备可以解码信息来允许色度频率控制从TVP5150设备数据在Genlock模式下以sclk的速率下被传输，在RTC模式下速率为SCLK/4O复用SDA22I2C数据总线I/OSCL21I2C时钟总线IYOUT0.718-11数据总线I/OYOUT(7)/I2CSEL11I2C地址选择，需要一个下拉或上拉寄存器，为1时地址为0xBA，为0时地址为0xB8YOUT7：ITUR BT.656 /YUV 422解码的最高有效位IXTAL15外部时钟参考IXTAL26外部时钟参考OCH1_AGND31模拟地IPLL_AGND3PLL接地,连接到模拟地IPLL_AVDD4PLL电源,连接到1.8V模拟电源IREEP29A/D参考电源通过一个1uF电容器连接到一个1uF参考地面IDGND19有源视频指标IDVDD20数字地面IRESETB8掉电端（低电平有效）。当被拉低时，重置所有的寄存器重启内部微处理器IREFM30A/D 参考地IREFP29A/D参考电源IPDN28电源关闭终端，让设备在备用模式，保存寄存器的值IPCLK/SCLK9系统时钟在1*或者2*像素时钟上OTVP5150寄存器设置：TVP5150内部寄存器通过I2C总线进行设置。I2C总线地址由I2CSEL引脚的高低电平决定。I2CSEL=1，写地址为0xBA；I2CSEL=0，写地址为0xB8。设置TVP5150内部一个寄存器的顺序如下：1. 主机发送开始信号；2. 主机发送TVP5150芯片地址；3. 从机应答；4. 主机发送TVP5150内部寄存器地址；5. 从机应答；6. 主机发送要写入TVP5150内部寄存器的数据；7. 从机应答；8. 主机发送停止信号；注意：当向TVP5150内部地址为00h-8Fh的寄存器写入时，在上述第7、8步骤间TVP5150芯片需要一个延时，用以等待数据写入寄存器。有两种方法判断是否数据写入寄存器：1、完成第7步后检测SCL总线的状态，当SCL总线为高时表示数据已写入寄存器，执行第8步；2、完成第7步后，等待64uS后执行第8步。这种设置在TVP5150AM1的芯片手册上的说明如下：I2C Host Interface：The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I2C system can be multimastered, the TVP5150 device functions as a slave device only.Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free,both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150 devices tied to the same I2C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used for the TVP5150 device, it can either pulled low or high through a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or VDD. Table 36 summarizes the terminal functions of the I2C-mode host interface.I2c主机接口I2C标准包含两个信号,串行输入/输出数据行(SDA)和输入/输出时钟线(sci),携带信息之间的设备连接到bus总线第三个信号(I2CSEL)是用于从设备地址的选择。尽管I2C系统可以有多个主设备，TVP5150设备功能作为一个从设备。SDA和sci必须通过一个上拉电阻连接到一个正电源电压。当BUS总线是空闲的时候,两条总线都是高电平。从设备地址选择终端(I2CSEL)使两个TVP5150设备到相同的I2C总线。在启动,I2CSEL状况的调查。根据写和读地址用于TVP5150装置,它通过一个电阻可以拉低或高。这个引脚与YOUT7多路复用,因此不能直接与地面或VDD连接。表36总结了引脚I2C模式主机接口的功能。I2C Host Port Timing：I2C Write OperationData transfers occur utilizing the following illustrated formats.An I2C master initiates a write operation to the TVP5150 device by generating a start condition (S) followed by the TVP5150 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle.After receiving an acknowledge from the TVP5150 device, the master presents the subaddress of the register,or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150 device acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P).I2c写操作利用数据传输发生以下所示格式。一个I2C主设备通过生成一个开始条件(S)发起一个写操作到TVP5150，然后是TVP5150 I2C地址(如下所示),在MSB第一位顺序,其次是0来表示写周期。在收到一个从TVP5150设备的回应后,主设备发出寄存器的内部地址。,或想写的块的第一个寄存器,紧随其后的是一个或多个字节的数据,最高有效位。的TVP5150设备回应每个传输完成后每个字节。I2C主设备通过产生一个停止条件(P)来终止写操作。I2C Read Operation：The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP5150 device by generating a start condition (S) followed by the TVP5150 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP5150 device, the master presents the subaddress of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P).The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5150 device by generating a start condition followed by the TVP5150 I2C address (as shown below for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from theTVP5150 device, the I2C master receives one or more bytes of data from the TVP5150 device. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP5150 device to the master, the master generates a not acknowledge followed by a stop.I2c读操作读操作由两个阶段组成。第一阶段是地址阶段。在这个阶段,一个I2C的主设备设备通过生成一个开始条件(S)发起一个写操作到TVP5150，接着是是TVP5150 的I2C地址,在MSB第一位顺序,其次是0来表示写周期。在收到回应后从TVP5150设备,主设备提出了寄存器的子地址或寄存器的第一块想读。周期是回应后,主设备立即终止循环通过生成停止条件(P)。第二阶段是数据阶段。在这个阶段,一个I2C TVP5150主发起一个读操作。设备通过生成一个开始,接下来TVP5150 I2C地址(阅读如下所示操作),在MSB第一位顺序,1表示一个读周期。在收到TVP5150设备的回应后,I2C主从TVP5150设备接收一个或多个字节的数据。I2C主设备回应传输的每个字节。最后一个数据字节后需要被传输从TVP5150设备到主设备,主设备会生成一个not acknowledge之后停止。Read Phase 1图：Read Phase 2图：I2C Timing RequirementsThe TVP5150 device requires delays in the I2C accesses to accommodate its internal processors timing. In accordance with I2C specifications, the TVP5150 device holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram。Normal register writing address 00h8Fh (addresses 90hFFh do not require delays)TVP5150设备需要延迟I2C访问,以适应其内部处理器的时机。在I2C规格,按照TVP5150将 I2C时钟线(sci)保持低电平等待I2C的主设备。如果I2C不是为了检查I2C时钟线held-low条件,然后最大延迟必须插入需要的地方。这些延迟是可变长度;最大延迟所示如下图:正常注册写地址00 h8fh (地址90 hFFh不需要延迟)Internal Control RegistersThe TVP5150 device is initialized and controlled by a set of internal registers which set all device operating parameters. Communication between the external controller and the TVP5150 device is through I2C. Table 38 shows the summary of these registers. The reserved registers must not be written. However,reserved bits in the defined registers must be written with 0s. The detailed programming information of each register is described in the following sections.TVP5150设备是由内部寄存器设置所有设备操作参数来初始化和控制。外部控制器通过I2C和TVP5150设备通信。表38显示了这些寄存器的总结。保留寄存器不能写。然而,在定义保留位寄存器必须用0。每个寄存器的详细的编程信息在以下部分中描述。R = Read only W = Write only R/W = Read and write代码中的寄存器设置：dsp文件夹的dsp_manual文件夹中的project文件夹中,tvp51XX.中,有如下代码:/* addr 00h - 07h */0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,1,0,0,1,0,1,1,0,0,0,0,0,0,0,0,0,0x10,0,0,0,0,1,0,0,/* addr 08h - 0fh */0,0,0,0,0,0x80,0x80,0,0x80,7,0,0,1,0,0,0,0,0,0,1,0,0,0,0,/* addr 10h - 17h */0,0,0,0,0,0,0,0,1,0,1,0,0,0,0x80,0,/* addr 18h - 1fh */0,0,0,1,1,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,/* addr 20h - 27h */0,0,0,0,0,0,0,0,/* addr 28h - 2fh */0,0,0,0,0,0,0,0x15,0x01,/* addr 30h - 7fh */0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,/* addr 80h - 87h */0x51,0x50,0x03,0x21,0,0,0,0,0,/* addr 88h - ffh */0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0在tvp51XX.h中,发现如下代码:备注是我添加上去的:/*typedef struct _TVP51XX_Generics/* Video Input Source Selection #1 (0x00) */ Uns svideo_sel : 1;/0 Uns channel1_sel : 1;/0 Unssource_sel_rsv1 : 1;/0 Uns black_output : 1;/0 Uns source_sel_rsv2: 4;/0/* Analog Channel Controls (0x01) */ Uns automatic_gain_ctrl : 2;/1 Uns automatic_offset_ctrl : 2;/1 Uns analog_channel_ctrl_rsv : 4;/1/* Operation Mode Controls (0x02) */ Uns power_down_mode : 1;/0 Uns luma_peak_disable : 1;/0 Uns color_subcarrier_pll_frozen : 1;/0 Uns white_peak_disable : 1;/0 Uns tv_vcr_mode : 2;/0 Uns color_burst_ref_disable : 1;/0 Uns operation_mode_ctrl_rsv : 1;/0/* Miscellaneous Control (0x03) */ Uns clock_output_enable : 1;/1 Uns vertical_blanking_onoff : 1/0; Uns hsync_vsync_output_enable : 1;/0 Uns ycrcb_output_enable : 1;/1 Uns lock_status : 1;/0 Uns gpcl_io_mode_sel : 1;/1 Uns gpcl : 1;/1 Uns vbko : 1;/0/* Autoswitch Mask (0x04) */ Uns autoswitch_mask_rsv1 : 2;/0 Uns palm_off : 1;/0 Uns paln_off : 1;/0 Uns n443_off : 1;/0 Uns sec_off : 1;/0 Uns autoswitch_mask_rsv2 : 2;/0/* Software Reset (0x05) */ Uns reset : 1;/0 Uns software_reset_rsv : 7;/0/* Color Killer Threshold Control (0x06) */ Uns color_killer_shreshold : 5;/0x10 Uns automatic_color_killer : 2;/0 Uns color_killer_shreshold_rsv: 1;/0/* Luminance Processing Control #1 (0x07) */ Uns luminance_signal_delay : 4;/0 Uns luma_bypass : 1;/0 Uns disable_raw_header : 1;/1 Uns pedestal_not_present: 1;/0 Uns luma_bypass_mode : 1;/0/* Luminance Processing Control #2 (0x08) */ Uns mac_agc_ctrl : 2;/0 Uns peaking_gain : 2;/0 Uns luminance_processing_ctrl_rsv1 : 2;/0 Uns luminance_filter_sel : 1;/0 Uns luminance_processing_ctrl_rsv2 : 1;/0/* Brightness Control (0x09) */ Uint8 brightness_ctrl;/0x80/* Saturation Control (0x0A) */ Uint8 saturation_ctrl;/0x80/* Hue Control (0x0B) */ Uint8 hue_ctrl;/0/* Contrast Control (0x0C) */ Uint8 contrast_ctrl;/0x80/* Outputs and Data Select (0x0D) */ Uns ycrcb_output_format : 3;/7 Uns ycrcb_data_path_bypass : 2;/0 Uns cbcr_code_format : 1;/0 Uns ycbcr_output_code_range : 1;/1 Uns outputs_data_sel_rsv : 1;/0/* Luminance Processing Control #3 (0x0E) */ Uns luminance_trap_filter_sel : 2;/0 Uns luminance_processing_ctrl_rsv3 : 6;/0/* Configuration Shared Pins (0x0F) */ Uns sclk_pclk : 1;/0 Uns intreq_gpcl_vblk : 1;/0 Uns vsync_pali : 1;/0 Uns fid_glco : 1;/1 Uns lock24b : 1;/0 Uns lock24a : 1;/0 Uns lock23 : 1;/0 Uns config_shared_pins_rsv : 1;/0/* Reserved (0x10) */ Uint8 rsv1;/0/* Active Video Cropping Start Pixel MSB (0x11) */ Uint8 avid_start_pixel_msb;/0/* Active Video Cropping Start Pixel LSB (0x12) */ Uns avid_start_pixel_lsb : 2;/0 Uns avid_active : 1;/0 Uns active_video_cropping_start_pixel_lsb_rsv : 5;/0/* Active Video Cropping Stop Pixel MSB (0x13) */ Uint8 avid_stop_pixel_msb;/0/* Active Video Cropping Stop Pixel LSB (0x14) */ Uns avid_stop_pixel_lsb : 2;/0 Uns active_video_cropping_stop_pixel_lsb_rsv : 6;/0/* Genlock and RTC (0x15) */ Uns glco_rtc : 1;/1 Uns genlock_rtc_rsv1 : 1;/0 Uns cdto_sw : 1;/1 Uns genlock_rtc_rsv2 : 1;/0 Uns fv_bit_ctrl : 2;/0 Uns genlock_rtc_rsv3 : 2;/0/* Horizontal Sync (HSYNC) Start (0x16) */ Uint8 hsync_start;/0x80/* Reserved (0x17) */ Uint8 rsv2;/0/* Vertical Blanking Start (0x18) */ Uint8 vertical_blanking_start;/0/* Vertical Blanking Stop (0x19) */ Uint8 vertical_blanking_stop;/0/* Chrominance Control #1 (0x1A) */ Uns automatic_color_gain_ctrl : 2;/0 Uns chrominance_comb_filter_enable : 1;/1 Uns chrominance_adaptive_comb_filter_enable : 1;/1 Uns color_pll_reset : 1;/0 Uns chrominance_control_rsv1 : 3;/0/* Chrominance Control #2 (0x1B) */ Uns chrominance_filter_select : 2;/0 Uns wcf : 1;/1 Uns chrominance_control_rsv2 : 1;/0 Uns chrominance_comb_filter_mode : 4;/1/* Interrupt Reset (0x1C) */ Uns tv_vcr_changed_reset : 1;/0 Uns hv_lock_changed_reset : 1;/0 Uns color_lock_changed_reset : 1;/0 Uns line_alternation_changed_reset : 1;/0 Uns field_rate_changed_reset : 1;/0 Uns command_ready_reset : 1;/0 Uns macrovision_detect_changed_reset : 1;/0 Uns software_initialization_reset : 1;/0/* Interrupt Enable (0x1D) */ Uns tv_vcr_changed : 1;/0 Uns hv_lock_changed : 1;/0 Uns color_lock_changed : 1;/0 Uns line_alternation_changed : 1;/0 Uns field_rate_changed : 1;/0 Uns command_ready : 1;/0 Uns macrovision_detect_changed : 1;/0 Uns software_initialization_occurred_enable : 1;/0/* Interrupt Configuration (0x1E) */ Uns interrupt_polarity_b : 1;/0 Uns interrupt_config_rsv : 7;/0/* Reserved (0x1F) - (0x27) */ Uint8 rsv39;/0/* Video Standard (0x28) */ Uns video_standard : 4;/0 Uns video_standard_rsv : 4/0/* Reserved (0x29) - (0x2B) */ Uint8 rsv43;/0/* Cb Gain Factor (0x2C) */ Uint8 cb_gain_factor;/0/* Cr Gain Factor (0x2D) */ Uint8 cr_gain_factor;/0/* Macrovision On Counter (0x2E) */ Uint8 macrovision_on_counter;/0x15/* Macrovision Off Counter (0x2F) */ Uint8 macrovision_off_counter;/0x01/* Reserved (0x30) - (0x7F) */ Uint8 rsv580;/0x0/* MSB of Device ID (0x80) */ Uint8 msb_of_device_id;/0x51/* LSB of Device ID (0x81) */ Uint8 lsb_of_device_id;/0x50/* ROM Version (0x82) */ Uint8 rom_version;/0x03/* RAM Patch Code Version (0x83) */ Uint8 ram_patch_code_version;/0x21/* Vertical Line Count MSB (0x84) */ Uns vertical_line_count_msb : 2;/0 Uns vertical_line_count_msb_rsv : 6;/0/* Vertical Line Count LSB (0x85) */ Uint8 vertical_line_count_lsb;/0/* Interrupt Status (0x86) */ Uint8 rsv6122;/0_TVP51XX_Generics;阅读其芯片手册,可得其寄存器每一位的定义如下:typedef struct _TVP51XX_Generics/* Video Input Source Selection #1 (0x00) */（视频输入源选择寄存器） Uns svideo_sel : 1;/0 Uns channel1_sel : 1;/0:AIP1A selected (default) Unssource_sel_rsv1 : 1;/0 Uns black_output : 1;/0 0 = Normal operation (default) Uns source_sel_rsv2: 4;/0 /* Analog Channel Controls (0x01) */（模拟频道控制寄存器） Uns automatic_gain_ctrl : 2;/1 01 = AGC enabled (default) （自动增益控制） Uns automatic_offset_ctrl : 2;/1 01 = Automatic offset enabled (default) （自动调整偏差） Uns analog_channel_ctrl_rsv : 4;/1 /* Operation Mode Controls (0x02) */（操作模式控制寄存器） Uns power_down_mode : 1;/0 0 = Normal operation (default) Uns luma_peak_disable : 1;/0 0 = Luma peak processing（亮度峰值处理） enabled (default) Uns color_subcarrier_pll_frozen : 1;/0 0 = Color subcarrier（辅助波） PLL（锁相环） increments by the internally generated phase increment. (default)GLCO pin outputs the frequency increment. Uns white_peak_disable : 1;/0 0 = White peak protection enabled (default) Uns tv_vcr_mode : 2;/0 00 = Automatic mode determined by the internal detection circuit. （内部检测电路）(default) Uns color_burst_ref_disable : 1;/0 0 = Color burst reference（色同步参考信号） for AGC （自动增益控制）disabled (default) Uns operation_mode_ctrl_rsv : 1;/0 /* Miscellaneous Control (0x03) */（混合控制寄存器） Uns clock_output_enable : 1;/1 1 = SCLK output is enabled (default) Uns vertical_blanking_onoff : 1/0; 0 = Vertical blanking (VBLK) （垂直消隐）off (default) Uns hsync_vsync_output_enable : 1;/0 0 = HSYNC（水平同步信号）, VSYNC（垂直同步）/PALI, AVID, and FID/GLCO are high-impedance（高阻抗）(default) Uns ycrcb_output_enable : 1;/1 1 = Y(OUT7:0) active Uns lock_status : 1;/0 0 = Terminal VSYNC/PALI outputs. PAL indicator (PALI) （PAL指示器信号）signal and terminal FID/GLCO outputs field ID（输出字段）(FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh) Uns gpcl_io_mode_sel : 1;/1 1 = GPCL is output Uns gpcl : 1;/1 GPCL outputs 1 Uns vbko : 1;/0 0 = GPCL (default) /* Autoswitch Mask (0x04) */（自动开关寄存器） Uns autoswitch_mask_rsv1 : 2;/0 Uns palm_off : 1;/0 0 = PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M. Uns paln_off : 1;/0 0 = PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N. Uns n443_off : 1;/0 0 = NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443. Uns sec_off : 1;/0 0 = SECAM is unmasked from the autoswitch process. Autoswitch d