SONY XR-C9100R汽车音响电路图纸.pdf

1 Model Name Using Similar MechanismXR C8100R Tape Transport Mechanism TypeMG 25D 136 SERVICE MANUALAEP Model UK Model XR C9100R FM MW LW CASSETTE CAR STEREO AEP UK Model FM MW SW CASSETTE CAR STEREO German Model Cassette player section Tape track4 track 2 channel stereo Wow and flutter0 08 WRMS Frequency response30 20 000 Hz Signal to noise ratio Cassette typeDolby B NRDolby C NRDolby NR off TYPE II IV67 dB73 dB61 dB TYPE I64 dB70 dB58 dB Tuner section FM Tuning range87 5 108 0 MHz Antenna terminalExternal antenna connector Intermediate frequency10 7 MHz Usable sensitivity8 dBf Selectivity75 dB at 400 kHz Signal to noise ratio65 dB stereo 68 dB mono Harmonic distortion at 1 kHz 0 7 stereo 0 4 mono Separation35 dB at 1 kHz Frequency response30 15 000 Hz MW LW AEP UK model Tuning rangeMW 531 1 602 kHz LW 153 281 kHz Aerial terminalExternal aerial connector Intermediate frequency10 71 MHz 450 kHz SensitivityMW 30 V LW 50 V MW SW German model Tuning rangeMW 531 1 602 kHz SW 5 950 6 205 kHz Aerial terminalExternal aerial connector Intermediate frequency10 71 MHz 450 kHz SensitivityMW 30 V SW 50 V Power amplifier section OutputsSpeaker outputs sure seal connectors Speaker impedance4 8 ohms Maximum power output45 W 4 at 4 ohms Continued on next page SPECIFICATIONS MICROFILM 29 6 3 IC PIN DESCRIPTION IC600 MB90574PFV G 134 BND SYSTEM CONTROL Pin No Pin NameI OPin Description 1SEKOUTOSEEK OUT output 2AF SEEKOAF SEEK output 3WIDEOWIDE NARROW select output 4ST MONOI OUse a thing both as ST IND display input and force MONO output 5TUNMUTEOTuner mute output 6FM ONOFM ON output 7TU ONOTuner ON output 8VCC Power supply pin 5 V 9ONNIN RSTOAudio composition IC reset output 10BUSONOBus ON control output 11SYSRSTOSystem reset output 12DOORSWIDoor OPEN CLOSE detection input 13LCDSOOLCD serial data output 14LCDCKOOLCD serial clock output 15BEEPOBEEP output 16LCDCEOLCD chip enable output 17UNISIISerial data input 18UNISOOSerial data output 19UNICKII OSerial clock input output 20ONNIN SIIAudio composition serial data input 21ONNIN SOOAudio composition serial data output 22ONNIN CKOOAudio composition serial clock output 23ONNIN CEOAudio composition chip enable output 24SIRCSIRemote commander input 25PLLSIIPLL data input 26PLLSOOPLL data output 27PLLCKOOPLL clock output 28PLLCEOPLL chip enable output 29ILL ONOIllumination power control output 30DIMMERODimmer control output 31TIRINDOTIR indicator control output 32LCDINHOLCD blank display control output 33VSS GND 34C Power stabilization capacitor pin 35AD ONOPower control output of A D conversion 36 37RE IN0 1IRotary encoder input 0 1 38DVCC D A converter VREF input 39DVSS GND of D A converter 40SD INISignal director input 41LCDANGOLCD view angle alignment output 42AVCC Analog power supply pin 5 V 43AVRH A D converter VREF input 44AVRL A D converter VREF input 45AVSS Analog GND 46 47KEYIN0 1IKey input 0 1 48RC IN0IRotary commander input 0 49ONNIN SW ON Audio composition IC power supply pin 5V 50DSTSEL1IFunction select input 51DSTSEL2ITuner destination setting input 52MTPITuner multi pass input Not used in this set 53VSMIS Meter voltage detection input 30 Pin No Pin NameI OPin Description 54VCC Power supply pin 5 V 55RAMBUIRAM reset detection input 56POWSELIPower select initial setting input 57EQ SELOEqualizer connection H 58TESTINITest mode setting detection input 59PACK INDODoor indicator output 60TIRPLAYOTIR playback audio line select output 61 62SUB SW1 0OSimple SUB WOOFER control output 1 0 63VSS GND 64VOLCEOElectric volume serial chip enable output 65MUTEOSystem mute control output 66VOLSO SUBSOOMain Sub volume serial data output 67VOLCKO SUBCKOOMain Sub volume serial clock output 68SUBCEOSub volume serial chip enable output 69FLASH WIFlash write in mode detection input 7012CSIOI ORDS serial data input output 7112CCKOORDS serial clock output 72RC IN1IRotary commander input 73X1A Low speed oscillation input 32 768 kHz 74X0A Low speed oscillation input 32 768 kHz 75DAVNIRDS IC data taking in detection input Not used in this set 76KEYACKIKey input acknowledge 77BU INIBack up power detection input 78ILLINIIllumination line detection input 79TELMUTEITelephone mute detection input 80NOSESWIFront panel detachable detection input 81ACCINIAccessory power detection input 82 85TIR D0 D1 D2 D3I OTIR IC command input output D0 D1 D2 D3 86HSTX Connect to power supply pin 87MD2IConnect to GND 88 89MD0 1IConnect to power supply pin 90RSTIMicrocomputer reset input 91VSS GND 92X0 High speed oscillation input 3 68 MHz 93X1 High speed oscillation input 3 68 MHz 94VCC Power supply pin 5 V 95TIR BUSYITIR IC BUSY output monitor pin 96TIR WROTIR IC data write pulse output 97TIR CEOTIR IC CE output 98TIR CEOTIR IC CE output 99TIR RESOTIR IC reset power down 100TIR PDOWNOTIR IC power down 101TIR RDOTIR IC data read pulse output 102MTLINIAuto METAL detection input 103AMSINITape AMS music detection input 104REELITape reel table rotation detection input 105POS0ITape position detection input 0 106POS1ITape position detection input 1 107POS2ITape position detection input 2 108POS3ITape position detection input 3 109LM EJOTape loading motor control output Eject direction 110LM LODOTape loading motor control output Loading direction 111CM ONOTape capstan motor control output 31 Pin No Pin NameI OPin Description 112TAPEONOTape power control output 113N ROUTOTape forward reverse detection output 114AMSONOTape AMS control output 115DOLBCOTape DOLBY B C select control output 116DOLBYOTape DOLBY control output 117ONNIN REQISpace condition indicate signal input for voice synthesizer IC 118LEDONOFront panel LED control output 119VSS GND 120POWONOSystem power control output 37 38 6 7 SCHEMATIC DIAGRAM MAIN SECTION 1 5 Refer to page 53 for IC Block Diagrams XR C9100R Page 42 Page 39 6 8 SCHEMATIC DIAGRAM MAIN SECTION 2 5 Refer to page 53 for IC Block Diagrams 39 40 XR C9100R 700 ILL ILL Page 38 Page 43 41 42 6 9 SCHEMATIC DIAGRAM MAIN SECTION 3 5 Refer to page 53 for IC Block Diagrams XR C9100R Page 46 Page 38 Page 43 6 10 SCHEMATIC DIAGRAM MAIN SECTION 4 5 Refer to page 53 for IC Block Diagrams 43 44 XR C9100R Page 42 Page 39 Page 47 Page 47 Page 48 Page 47 45 46 6 11 SCHEMATIC DIAGRAM MAIN SECTION 5 5 Refer to page 53 for IC Block Diagrams XR C9100R Page 41 48 XR C9100R 6 13 SCHEMATIC DIAGRAM INVERTER SUB SECTION D899 MA8062M Page 44 Page 44 Page 44 Page 51 Page 44 6 15 SCHEMATIC DIAGRAM DISPLAY SECTION 51 52 XR C9100R Page 48 53 54 PHASE DET PRESCALER MAIN COUNT IF COUNT CTL 20BIT COUNT SHIFT REGISTER LATCH REFERENCE DIVIDER I O CTL 1 2 4 5 6 7 9 10 20 18 17 16 15 14 13 12 11 19 XIN CE CK DA CD P0 P1 P3 XOUT VSS PD VDD FMIN AMIN P2 IFIN SD P4 IC Block Diagrams IC10 BU2624FV E2 IC100 MSM6688GS 1 2 3 4 42 41 40 39 38 37 36 32 31 30 29 35 34 33 5 6 7 8 9 10 12 13 14 11 151617 1819 20 21 22 23 2425262728 4344454748495052535455565146 MCU I F STATUS REGISTER TEST CIRCUIT 12BIT ADC LPF 12BIT DAC SG CIRCUIT ADDRESS CONTROLLER ADPCM ANALYZER SYNTHESIZER TIMING CONTROLLER OSC DATA I O REGISTER CONTROLLER D0 D1 D2 D3 BUSY RPM VPM TEST TEST TEST TEST MCUM CE ACON CS3 CS2 CS1 SADX SADY PDWN TEST AGND RSEL2 RSEL1 DGND TEST TEST ADIN FOUT AOUT FIN AMON DVDD AVDD SG SGC LOUT LINE MOUT MIN CE WR RD RESET NAR RWCK DVDD XT XT WE DROM DI 0 CS4 TAS SAS MON REFERENCE REFERENCE VCCL VCCL VCCL INL SVRL INML INMR SVRR INR VCCR VCCR VCCR BUFFER BUFFER BUFFER BUFFER LIFT AMP SIGNAL AMP LIFT AMP SIGNAL AMP CL CL LGND OUTL OUTR RGND CR CR 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 IC310 410 TDA8574 T TIMING GENERATOR 8 388 608DATA REGISTER COLUMN DECODER COLUMN ADDRESS COUNTER ROW DECODER ADDRESS MULTIPLEXER REFRESH ADDRESS COUNTER ROW ADDRESS COUNTER ROW ADDRESS REGISTER REFRESH TIMER I O CONTROL WRITE CLOCK GENERATOR 2 3 4 5 11 12 13 10 9 1 25 24 23 22 18 17 16 15 14 26 TEST RWCK NC TEST TEST TEST TEST DIN NC VSS VCC RS A RFSH SAD SAS TAS CS WE DOUT NC OVER VOLTAGE PROTECT REGULATOR 123456789101211 NC MODE2 MODE1 STB VDD AMP VCC ANT COM AM FM GND 1 2 3 4 5 6 78 9 10 14 13 12 11 BUS ON SWITCH RESET SWITCH BATTERY SWITCH BUS ON RST BATT CLK VREF DATA GND VCC RST BUS ON CLK IN BU IN DATA IN DATA OUT 1 2 3 4 56 7 8 9 10GND IN1 VCC IN2 GNDN C OUT2 VS OUT1 N C CONTROL LOGIC IC201 LB1638MTP T2 IC502 BA3918 V3IC602 BA8270F E2 IC150 SAA6588 11 12 13 10 9 8 7 6 5 4 3 1 2 20 18 17 16 15 14 19 PAUSE DETECTOR INTERFACE REGISTER RDS RDBS DECODER OSCILLATOR AND CLOCK TEST CONTROL MULTI PATH DETECTOR RDS RDBS DEMODULATOR CLOCKED COMPARATOR POWER SUPPLY AND RESET 57kHz 8th ORDER BAND PASS SIGNAL QUALITY DETECTOR IIC BUS SLAVE TRANSCEIVER SCL SDA DAVN VDDD VSSD OSCI OSC0 TCON MPTH MRO LVIN CIN SCOUT VREF MPX VSSA VDDA AFIN MAD PSWN 5 4 4 IC101 MSM6685JSDR1 IC501 RN5VD33AA TL 123 45 CD NC OUT VDD GND RESET 55 37GAIN12 38GAIN11 39IN14 40IN13 41IN12 42IN11 INPUT SW 36 GAIN134 LOUD VOLUME 8dB STEP VOLUME 1dB STEP TONEFADER 35 LDLC1 34 LDHC1 33 INAO1 32 VRIN1 31 VOUT1 30 TIN1 29 TCLC1 28 TCLC11 27 TCLC12 26 TCO1 25 FDIN1 24 FNTO1 23 REO1 VCTBUFF VCTBUFF VCTBUFF LATCH CONTROL LATCH 1 GAIN234 LOUD VOLUME 8dB STEP VOLUME 1dB STEP TONEFADER 2 LDLC2 3 LDHC2 4 INAO2 5 VRIN2 6 VOUT2 7 TIN2 8 TCLC2 9 TCLC21 10 TCLC22 11 TCO2 12 FDIN2 14 REO2 13 FNTO2 VCTBUFF VCTBUFF VCTBUFF SHIFT REGISTER ZCDET 43IN21 44IN22 45IN23 46IN24 47GAIN21 48GAIN22 INPUT SW 18 VCC 17 VCT 16 DATA 15 TIMER 22 CE 21 CLK 20 DGND 19 GND 45k 45k 20 19181716151413 12 11 123456789 10 1dB STEP VOLUME 8dB STEP VOLUME 1dB STEP VOLUME 8dB STEP VOLUME VCT BUFFER LATCH SHIFT REGISTER LATCH CONTROL ZC DET INP 1 INN 1 VCT 1 INAO 1 VRIN 1 OUT 1 N C GND VCT VCC INP 2 INN 2 VCT 2 INAO 2 VRIN 2 OUT 2 CE DATA CLK INIT 31 30292827262524232221 20 19 18 17 16 15 14 13 12 11 32 33 34 35 36 37 38 39 40 NR NR NR BIAS TAPE AUX TAPE EQ FWD RVS MS MODE NR MODE DET 10987654321 LPF VCT T2 X1 X1 T1 F3 VCC OFF B C OFF B C F1 F2 120 70 120 70 MS ON OFF PBFB2 PBRIN2 PBREF2 PBFIN2 VCT PBGND PBFIN1 PBREF1 PBRIN1 PBFB1 PBEQ1 PBOUT1 VCC TAPEIN1 AUXIN1 MSLPF LINEOUT1 TCH1 TCL1 G2FB PBEQ2 PBOUT2 GND TAPEIN2 AUXIN2 DIREF LINEOUT2 TCH2 TCL2 MSSW MSMODE DRSW TAPESW INSW NRSW NRMODE MSOUT DGND MSTC G1FB IC250 CXA2511AQIC350 CXA1846N T4 IC301 CXA1946BQ T6 56 CONTROL CIRCUIT LOW VCC DETECTOR CIRCUIT WRITE ERASE PULSE TIMER ERASE CIRCUIT RY BY BUFFER CHIP ENABLE OUTPUT ENABLE CIRCUIT I O BUFFER DATA LATCH ADDRESS LATCH Y DECODER 8 388 608 CELL MATRIX Y GATE WRITE CIRCUIT 23 2425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ7 DQ14 DQ6 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 GND CE OE 1 2 3 4 5 6 7 8 9 10 20