i5处理器移动芯片组HM55主板图纸GE5-v01.pdf

5 5 4 4 3 3 2 2 1 1 DD CC BB AA Initial Date Drawing by Nick Wu Board name Mother Board Schematic Version 0 1 Leader Sign by Gary Yang Total confirm by PAGE 01 Title Project GE5 Calpella Platform PAGE 02 Block diargram PAGE 03 CPU DMI PEG FDI 1 PAGE 04 CPU CLK MISC JTAG 2 PAGE 06 CPU POWER 4 PAGE 07 CPU Graphic Power 5 PAGE 08 CPU Ground 6 PAGE 05 CPU DDR3 3 PAGE 10 Thermal Fan Control PAGE 11 Clock Generator PAGE 12 DDR3 SDRAM SO DIMM0 PAGE 09 CPU Reserved 7 PAGE 17 PCH LVDS DDI 4 PAGE 18 PCH PCI USB NVRAM 5 PAGE 19 PCH GPIO NCTF RSVD 6 PAGE 21 PCH POWER 8 PAGE 20 PCH POWER 7 PAGE 13 DDR3 SDRAM SO DIMM1 PAGE 14 PCH HDA JTAG SATA 1 PAGE 15 PCH PCI E SMBUS CLK 2 Page Description PAGE 16 PCH DMI FDI GPIO 3 PAGE 22 PCH Ground 9 PAGE 23 Reset Circuit PAGE 40 SDVO TO DVI SIL1362 PAGE 41 LED Board PAGE 43 ODD BOARD PAGE 42 IO Board MIC IN CNN PAGE 32 EC IT8502E PAGE 44 POWER BLOCK PAGE 33 DCIN Screw Hole PAGE 39 VGA CORE 1 8VDDM First International Computer Inc HW Design Team II Project Code P09C00 PAGE 31 HDD ODD PAGE 34 3 5PMU VDDM PAGE 35 1 5VDDS M 0 75VDDS PAGE 36 1 1VDDM VTT 1 05VDDM PAGE 37 CPU Core Power PAGE 38 Gfx VGA Power PAGE 28 LAN RTL 8111DL PAGE 27 Audio ALC 662 PAGE 26 Card Reader AU6433 GEF PAGE 30 USB PAGE 29 Mini Card Wirless LAN PAGE 25 HDMI Port CNN PAGE 24 CRT Title P09C00 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 144Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Intel PCH BD82HM55 904529 FCBGA 1071 Pin Ver B3 Dual Channel DDR3 1 5V Dual Channel DDR3 1 5V GE5 Block Diagram HDMI CONNECTOR DVI CONNECTOR Arrandale Series SODIMM1 Processor SODIMM0 DMI 4 Banndwidth 2G TX 1G RX 1G DMI 4 Banndwidth 2G TX 1G RX 1G Intel SATA Gen 1 Keep 20 mils spacing to other signals to minimize crosstalk PROCESSOR DMI PGE FDI P09C00 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 344Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc EXP RBIAS FDI TXN0 FDI TXN1 FDI TXN2 FDI TXN3 FDI TXN4 FDI TXN5 FDI TXN6 FDI TXN7 FDI TXP0 FDI TXP1 FDI TXP2 FDI TXP3 FDI TXP4 FDI TXP5 FDI TXP6 FDI TXP7 PEG IRCOMP R DMI TXN0 16 DMI TXN1 16 DMI TXN2 16 DMI TXN3 16 DMI TXP0 16 DMI TXP1 16 DMI TXP2 16 DMI TXP3 16 DMI RXN0 16 DMI RXN1 16 DMI RXN2 16 DMI RXN3 16 DMI RXP0 16 DMI RXP1 16 DMI RXP2 16 DMI RXP3 16 FDI TXN 7 0 16 FDI TXP 7 0 16 FDI FSYNC0 16 FDI FSYNC1 16 FDI INT 16 FDI LSYNC0 16 FDI LSYNC1 16 PCI EXPRESS GRAPHICS DMIIntel R FDI U2A mPGA989B A24 C23 B22 A21 B24 D23 B23 A22 D24 G24 F23 H23 D25 F24 G23 E23 E22 D21 D19 D18 G21 E19 F21 G18 D22 C21 D20 C18 G22 E20 F20 G19 F17 E17 C17 F18 D17 B26 A26 A25 B27 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 DMI RX 0 DMI RX 1 DMI RX 2 DMI RX 3 DMI RX 0 DMI RX 1 DMI RX 2 DMI RX 3 DMI TX 0 DMI TX 1 DMI TX 2 DMI TX 3 DMI TX 0 DMI TX 1 DMI TX 3 DMI TX 2 FDI TX 0 FDI TX 1 FDI TX 2 FDI TX 3 FDI TX 4 FDI TX 5 FDI TX 6 FDI TX 7 FDI TX 0 FDI TX 1 FDI TX 2 FDI TX 3 FDI TX 4 FDI TX 5 FDI TX 6 FDI TX 7 FDI FSYNC 0 FDI FSYNC 1 FDI INT FDI LSYNC 0 FDI LSYNC 1 PEG ICOMPI PEG ICOMPO PEG RBIAS PEG RCOMPO PEG RX 0 PEG RX 1 PEG RX 2 PEG RX 3 PEG RX 4 PEG RX 5 PEG RX 6 PEG RX 7 PEG RX 8 PEG RX 9 PEG RX 10 PEG RX 11 PEG RX 12 PEG RX 13 PEG RX 14 PEG RX 15 PEG RX 0 PEG RX 1 PEG RX 2 PEG RX 3 PEG RX 4 PEG RX 5 PEG RX 6 PEG RX 7 PEG RX 8 PEG RX 9 PEG RX 10 PEG RX 11 PEG RX 12 PEG RX 13 PEG RX 14 PEG RX 15 PEG TX 0 PEG TX 1 PEG TX 2 PEG TX 3 PEG TX 4 PEG TX 5 PEG TX 6 PEG TX 7 PEG TX 8 PEG TX 9 PEG TX 10 PEG TX 11 PEG TX 12 PEG TX 13 PEG TX 14 PEG TX 15 PEG TX 0 PEG TX 1 PEG TX 2 PEG TX 3 PEG TX 4 PEG TX 5 PEG TX 6 PEG TX 7 PEG TX 8 PEG TX 9 PEG TX 10 PEG TX 11 PEG TX 12 PEG TX 13 PEG TX 14 PEG TX 15 R1849 9 1 0402 R17750 1 0402 5 5 4 4 3 3 2 2 1 1 DD CC BB AA ARRANDALE CLARKFIELD PROCESSOR CLK MISC JTAG ARRANDALE CLARKFIELD PROCESSOR CLK MISC JTAG Processor JTAG MAPPINGJTAG MAPPING Scan Chain Default CPU Only GMCH Only STUFF R193 R194 R217 NO STUFF R195 R216 STUFF R193 R195 NO STUFF R194 R216 R217 STUFF R216 R217 NO STUFF R193 R194 R195 PUll UP SIGNALSCOMPENSATIONPUll UP SIGNALSCOMPENSATION All COMP use 10 mils trace width for routing less than 500 mils or 20 mils trace width for routing between 500 and 1000 mils Keep 20 mils spacing to other signals to minimize crosstalk DDR3 PROCESSOR CLK MISC JTAG P09C00 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 444Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc H COMP3 H COMP2 H COMP1 H COMP0 H CATERR PLT RST R DDR3 DRAMRST SM RCOMP 0 SM RCOMP 1 SM RCOMP 2 PM EXTTS 1 XDP PREQ XDP TCLK XDP TMS XDP TRST XDP TDI R XDP TDO R XDP TDI M XDP TDO M XDP DBRESET H CPURST R 1 1VDDM VTT H COMP0 H COMP1 H COMP2 H COMP3 SM RCOMP 1 SM RCOMP 0 SM RCOMP 2 XDP TMS XDP TDI R XDP PREQ XDP TCLK XDP TDI XDP TDO R XDP TDI R XDP DBRESET 3VDDM PM EXTTS 0 PM EXTTS 0 XDP TRST XDP TDO PCH DRAM PWRGD PMU3V DDR3 DRAMRST 1 5VDDS H PROCHOT D H THRMTRIP R XDP TDI M XDP TDO M PM EXTTS 1 H CATERR H PROCHOT D H CPURST R XDP TDO R H PECI 19 H PROCHOT 32 37 H THRMTRIP 19 H PM SYNC 16 H CPUPWRGD 19 PCH DRAM PWRGD 16 EC VTTPWRGD 32 PLTRST 18 28 29 32 40 PM EXTTS 1 R 12 13 BCLK CPU P 19 BCLK CPU N 19 CLK EXP P 15 CLK EXP N 15 1 1VDDM VTT 6 7 19 20 21 36 37 CLK DP P 15 CLK DP N 15 3VDDM 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 32 34 36 37 38 39 40 PMU3V 14 15 16 18 19 21 23 28 29 30 32 33 34 35 DDR3 DRAMRST 12 13 1 5VDDS 7 12 13 34 35 3VDDM 1 1VDDM VTT 1 5VDDS 1 1VDDM VTT 1 5VDDS PMU3V 1 1VDDM VTT 3VDDM 1 5VDDS CLOCKS MISCTHERMAL PWR MANAGEMENT DDR3 MISC JTAG An external Display Port device is connected to the Embeded Display Port CFG4 1 Disabled No Physical Display Port attached to Embeded Display Port CFG Straps for ProcessorCFG Straps for Processor VSS AP34 can be left NC is CRB implementation EDS DG recommendation to GND VSS AP34 can be left NC is CRB implementation EDS DG recommendation to GND 0311 PDG V1 5 Update CFG Straps for ProcessorCFG Straps for Processor CFG0 1 Single PEG 0 Bifurcation enabled PCI Express Configuration Select PCI Express Select Lane Reversal Display Port Presence PROCRESS RESERVED P09C00 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 944Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc TP RSVD18 R CFG0 CFG3 CFG4 CFG7 TP RSVD17 R TP RSVD64 R TP RSVD65 R CFG7 CFG0 CFG4 CFG3 TP RSVD86 R RSVD35 RSVD33 RSVD32 RSVD36 RSVD41 CPU DIMM1 VREF 13 CPU DIMM0 VREF 12 R483 01K 1 0402 N TP15 1 TP14 1 R350 5 0402 N TP13 1 R2893 01K 1 0402 N RESERVED U2E mPGA989B AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 AH25 AK26 AJ26 AT3 AJ27 AP1 AT2 AR1 H16 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 C35 B35 A34 A33 J28 J29 A19 B19 A20 B20 T9 U9 AB9 AC9 C1 A3 AA5 AA4 R8 AA2 AA1 R9 AD3 AG7 AD2 AE3 V4 V5 N2 W3 W2 N3 AD5 AE5 AD7 AD9 AL26 AR2 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 AJ13 AJ12 E15 F15 A2 D15 C15 AJ15 AH15 AP34 CFG 0 CFG 1 CFG 2 CFG 3 CFG 4 CFG 5 CFG 6 CFG 7 CFG 8 CFG 9 CFG 10 CFG 11 CFG 12 CFG 13 CFG 14 CFG 15 CFG 16 CFG 17 RSVD34 RSVD35 RSVD38 RSVD NCTF 42 RSVD39 RSVD NCTF 40 RSVD NCTF 41 RSVD NCTF 43 RSVD TP 86 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD NCTF 54 RSVD NCTF 55 RSVD NCTF 56 RSVD NCTF 57 RSVD58 RSVD NCTF 30 RSVD NCTF 31 RSVD NCTF 28 RSVD NCTF 29 RSVD27 RSVD26 RSVD16 RSVD15 RSVD17 RSVD18 RSVD20 RSVD19 RSVD22 RSVD21 RSVD NCTF 23 RSVD NCTF 24 RSVD TP 66 RSVD TP 67 RSVD TP 68 RSVD TP 71 RSVD TP 72 RSVD TP 73 RSVD TP 69 RSVD TP 74 RSVD TP 70 RSVD TP 75 RSVD TP 76 RSVD TP 77 RSVD TP 78 RSVD TP 81 RSVD TP 82 RSVD TP 83 RSVD TP 79 RSVD TP 84 RSVD TP 80 RSVD TP 85 RSVD36 RSVD NCTF 37 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA DIMM VREF SB DIMM VREF RSVD11 RSVD12 RSVD13 RSVD14 RSVD32 RSVD33 RSVD TP 59 RSVD TP 60 KEY RSVD62 RSVD63 RSVD64 RSVD65 VSS R190 0402 N R160 0402 N R493 01K 1 0402 N TP12 1 R296SHW 0 5 1 16W 0402 N R2863 01K 1 04 N R340 0402 N TP5 1 5 5 4 4 3 3 2 2 1 1 DD CC BB AA System Thermal Sensor Fan CONN THERMAL SENSORTHERMAL SENSOR V0 2 0814 change to TMP431B Accuracy 1 C 60 C to 100 C remote 3 C 60 C to 100 C local Address 100 1101 LDO FAN COMTROLLDO FAN COMTROL Pls check with spec of 3 PIN FAN connector 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 1044Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc THER S D THER S D 5VDDM 15 17 20 21 23 25 31 33 34 36 37 38 39 40 3VDDM 4 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 32 34 36 37 38 39 40 MMB SMDAT 32 MMB SMCLK 32 FAN PWM 32 FAN SPEED 32 3VDDM 5VDDM 5VDDM 3VDDM C259 2 2uF 10V 0603 C83 0 1UF 16V 0402 U4 LNR IC Temperature Sensor TMP431BDGKR 2 7 5 5V MSOP 8 8PIN TI LR 1 2 3 45 6 7 8 VCC D D THM GND ALRT SDATA SCLK Q11 TRANS NPN MMBT3904 40V 200mA SOT 23 3PIN B EC C255 2 2uF 10V 0603 R68 10 5 1 10W SMT0603 LR U13 LNR IC FAN DRIVER 1 6X RT9027BPS 1 2 3 45 6 7 8 VEN VIN VO VSETGND GND GND GND CN18 CON ACES SMT TYPE 85205 03001 WIRE 1 25P 3PIN LR DO NT CARE 20 24197 20 1 2 3 4 5 C240 0 22uF 10V 0603 R21510K 0402 5 5 4 4 3 3 2 2 1 1 DD CC BB AA CPU 0 Default 0311 change to NU 0424 ADD PD 0430 ADD CAP for EMI stuff X TAL In and PD CAP Clock Enable CPU Freqency Straps CLOCK GENERATOR X TAL In and PD CAP Clock Enable CPU Freqency Straps CLOCK GENERATOR CPU 1 Near U53 Pin RF Solution Pin30 0 1 133MHz 100MHz 133MHz 100MHz Clock Generator P09C00 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 1144Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc CLK GPU 27M SSIN CLK 48M CR 1 05VDDM CR 48M CKPWRGD CLK 27FIXCLK 27FIX CLK 27SSCLK 27SS CPU BSEL 3VDDM XTAL IN CLK GPU 27M CLK BUF REF14 XTAL OUT CKPWRGD XTAL OUT CPU BSELCPU BSEL CK CPU STOP XTAL IN CLK BUF BCLK P 15 SMB DATA M 12 13 15 29 CLK BUF DOT96 P 15 CLK BUF BCLK N 15 CLK GPU 27M SSIN SMB CLK M 12 13 15 29 VR PWRGD CLKEN 37 CLK BUF EXP N 15 CLK BUF REF14 15 CLK GPU 27M CLK BUF CKSSCD N 15 CLK BUF EXP P 15 1 05VDDM 14 15 16 20 21 36 3VDDM 4 10 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 32 34 36 37 38 39 40 CLK BUF CKSSCD P 15 CLK 48M CR 26 CLK BUF DOT96 N 15 VDD CK505 3VDDM 1 05VDDM VDDIO CLK VDD CK505 VDD CK505 1 05VDDM 3VDDM VDD CK505 C523 0 1uF 16V 0402 C4785pF 50V 04 N U24 ASIC CLOCK GENERATOR ICS9LRS3199AKLFT MLF 32PIN VER A IDT LR 1 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 VDD48Mhz 3 3 USB48Mhz GND48Mhz DOT96T LPR DOT96C LPR VDD 27MHz 27MHz nonSS 27MHz SS GND27Mhz SATAT LPR SATAC LPR GNDSRC SRCT1 LPR SRCC1 LPR VDDSRC IO CPU STOP VDDSRC 3 3 VDDCPU IO CPUC1 LPR CPUT1 LPR GNDCPU CPUC0 LPR CPUT0 LPR VDDCPU 3 3 CLKPWRGD PD 3 3 GNDREF X2 X1 VDDREF 3 3 REF 3L FSLC 3 3 SDATA 3 3 SCLK 3 3 GND R402 10K 0402 N C541 33pF 50V 20 SMT0402 NPO LR C529 33pF 50V 20 SMT0402 NPO LR C4875pF 50V 0402 L34 600 1000mA 0603 R442 100K 1 1 16W SMT0402 LR C4885pF 50V 0402 L36600 1000mA 0603 R42033 0402 R39633 0402 R3950 0402 R455 10K 0402 C570 0 1uF 16V 0402 R409 10K 0402 C477 5pF 50V 04 N Q40 NPN RT1N441M T111 1 50V 100mA SC 70 3PIN EC B C4865pF 50V 0402 C575 5pF 50V 04 N C533 0 1uF 10V 0402 C545 10uF 6 3V 0805 R39733 0402 C568 0 1uF 16V 0402 Y5 X TAL 14 318180MHz 20pF 30PPM 2PIN SMT8 0 4 5 1 4mm F81430020 eCERA LR C491 10uF 6 3V 0805 C5175pF 50V 0402 C495 0 1uF 16V 0402 C569 0 1uF 10V 0402 C496 0 1uF 16V 0402 R449 10K 0402 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Guide 1x 12m ohm 330uF Place one to each SO DIMM 6x 0603 10uF per DIMM Schematic 1x 7343 330uF 8x 0805 10uF 4x 0402 0 1uF Guide 4x 0402 1uF per DIMM 3x 0805 0603 10uF Shared between the two DIMMs Place two capacitors close to the VR and one between the two DIMMs Schematic 4x 0603 1uF 3x 0805 10uF Decoupling Cap Decoupling Cap DDR3 SO DIMM VREF DQ ImplementationDDR3 SO DIMM VREF DQ Implementation M1 M3 SPD TS AddressSPD TS Address SPD is 0 xA0h TS is 0 x30h 0310 design guide 1 5 remove M2 For Arrandale M1 should be used For Clarksfield M3 should be used 0316 design guide 1 51 M1 M3 support at on time MoW WW11Update Removal M2 Method V0 2 0801 Change to NU BLOCK 4 12mils12mils DDR III SDRAM SO DIMM0DDR III SDRAM SO DIMM0 including data signals Memory Channel Signal NamesDesign Rule including data signals Memory Channel Signal NamesDesign Rule Channel A Channel B DQ 16 18 36 42 56 57 60 61 62 V0 2 0814 change NET V0 2 0804 VREFDQ Should Be Maintained within Spec during S3 FET is uied toisolate VREF form CPU to memory during suspend DQ 15 32 48 54 DM 5 Reguires minimum Spacing with all other signals DDR III SDRAM SO DIMM0 P09C00 0 1 5FL NO 300 Yang Guang St NeiHu 114 TAIPEI TAIWAN ROC 886 2 8751 8751 C 1244Wednesday December 02 2009 GE5 Intel Calpella Title SizeDocument NumberRev Date Sheetof First International Computer Inc DDR 0 75VDDM 1 5VDDS 3VDDM SA1 DIM0 SA0 DIM0 M A A3 M A DM7 M A DM6 M A DM4 M A DM5 M A DM2 M A DM0 M A DM1 M A A7 M A A6 M A A4 M A A5 VREF DQA M A DQS3 M A DQS7 M A DQS6 M A DQS4 M A DQS5 M A DQS2 M A DQS0 M A DQS1 M A DQS 3 M A DQS 7 M A DQS 6 M A DQS 4 M A DQS 5 M A DQS 2 M A DQS 0 M A DQS 1 M A DQ3 EVENT A M A A2 M A DQ7 M A DQ6 M A DQ4 M A DQ5 M A DQ2 M A DQ15 M A DQ14 M A DQ12 M A DQ13 M A DQ10 M A DQ8 M A DQ9 M A DQ0 M A DQ1 M A DQ11 M A DQ19 M A DQ23 M A DQ22 M A DQ20 M A DQ21 M A DQ18 M A DQ27 M A DQ31 M A DQ30 M A DQ28 M A DQ29 M A DQ26 M A DQ24 M A DQ25 M A DQ16 M A DQ17 M A A11 M A A15 M A A14 M A A12 M A A13 M A A10 M A A8 M A A9 M A DQ35 M A DQ39 M A DQ38 M A DQ36 M A DQ37 M A DQ34 M A DQ43 M A DQ47 M A DQ46 M A DQ44 M A DQ45 M A DQ42 M A DQ40 M A DQ41 M A DQ32 M A DQ33 M A DM3 M A DQ51 M A DQ55 M A DQ54 M A DQ52 M A DQ53 M A DQ50 M A DQ59 M A DQ63 M A DQ62 M A DQ60 M A DQ61 M A DQ58 M A DQ56 M A DQ57 M A DQ48 M A DQ49 SA0 DIM0 SA1 DIM0 M A A0 M A A1 M VREF VREF DQAM VREF A 3VDDM 4 10 11 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 32 34 36 37 38 39 40 1 5VDDS 4 7 13 34 35 DDR 0 75VDDM 13 35 M A A 15 0 5 M A BS0 5 M A BS1 5 M A BS2 5 M CS 0 5 M CS 1 5 M CLK DDR0 5 M CLK DDR1 5 M CLK DDR 0 5 M CLK DDR 1 5 M CKE0 5 M CKE1 5 M A CAS 5 M A RAS 5 M A WE 5 SMB DATA M 11 13 15 29 SMB CLK M 11 13 15 29 M ODT0 5 M ODT1 5 M A DM 7 0 5 M A DQS 7 0 5 M A DQS 7 0 5 DDR3 DRAMRST 4 13 M A DQ 63 0 5 PM EXTTS 1 R 4 13 DRAMRST CNTRL PCH 13 19 M VREF 13 35 CPU DIMM0 VREF 9 1 5VDDS 3VDDM M VREF DDR 0 75VDDM 1 5VDDS 1 5VDDSDDR 0 75VDDM M VREF 3VDDM 1 5VDDS DDR 0 75VDDM C4231uF 6 3V 0603 R33710K 0402 C34710uF 6 3V 0805 R2320 0402 N C4311uF 6 3V 0603 C434 2 2uF 6 3V 0603 C384 2 2uF 6 3V 0603 C3430 1uF 10V 0402 N C37710uF 6 3V 0805 C4141uF 6 3V 0603 R34110K 0402 C266 2 2uF 6 3V 0603 C381 0 1uF 10V 0402 C36010uF 6 3V 0805 N C36710uF 6 3V 0805 R243 1K 0402 C3730 1uF 10V 0402 N C3230 1uF 10V 0402 N C33510uF 6 3V 0805 C425 0 1uF 10V 0402 R233 100K 0402 C49330uF 2V 7343 R2420 0402 C5010uF 6 3V 0805 N C4221uF 6 3V 0603 C3330 1uF 10V 0402 N R3380 0402 Q23 TRANS M FET N BSS138 NL 50V 0 22A SOT 23 3PIN FAIRCHILD LR D G S C43810uF 6 3V 0805 STD TYPE CN6 CON CONCRAFT 0706A1BA92E SMD DDRIII 204PIN P 0 6 H 9 2 REV LR 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 98 97 96 95 92 91 90 86 89 85 107 84 83 119 108 109 101 103 102 104 73 74 115 110 113 114 121 197 201 202 200 11 28 46 63 136 153 170 187 12 29 47 64 137 154 171 188 75 76 81 82 87 88 93 94 99 100 105 106 199 30 77 122 125 2 3 8 9 13 14 111 112 117 118 123 80 78 116 120 10 27 45 62 135 152 169 186 1 126 79 124 198 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 203 204 205 206 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 BC A13 BA1 BA0 CK0 CK0 CK1 CK1 CKE0 CKE1 CAS RAS WE S0 S1 SA0 SA1 SCL SDA DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD RESET NC1 NC2 NCTEST VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VDD13 VDD14 VDD15 VDD16 VDD17 A14 A15 ODT0 ODT1 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 VREF DQ VREF CA BA2 VDD18 EVENT VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VTT1 VTT2 G1 G2 C37510uF 6 3V 0805 R238 1K 0402 C32710uF 6 3V 0805 C271 0 1uF 10V 0402 5 5 4 4 3 3 2 2 1 1 DD CC BB AA DDR III SDRAM SO DIMM1DDR III SDRAM SO DIMM1 12mils including data signals Memory Channel Signal NamesDesign Rule 12mils including data signals Memory Channel Signal NamesDesign Rule Channel A Channel B DQ 15 32 48 54 DM 5 DQ 16 18 36 42 56 57 60 61 62 Guide 4x 0402 1uF per DIMM 3x 0805 0603 10uF Shared between the two DIMMs Place two capacitors close to the VR and one between the two DIMMs Schematic 4x 0603 1uF 3x 0805 10uF Decoupling Cap Decoupling Cap Guide 1x 12m ohm 330uF Place one to each SO DIMM 6x 0603 10uF per DIMM Schematic 1x 7343 330uF 8x 0805 10uF 4x 0402 0 1uF DDR3 SO DIMM VREF DQ ImplementationDDR3 SO DIMM VREF DQ Implementation M