数字钟实验报告.docx

多功能数字钟电路设计实验报告 自动化1107班 XXX U201113XXX 一、实验目的1、 掌握数字电路系统的设计方法、装调技术及数字钟的功能扩展电路的设计；2、 掌握Quartus 编程，实用Verilog HDL语言设计数字钟。二、实验原理1、 数字钟的功能要求： 基本功能为： 准确计时，以数字形式显示时、分、秒的时间； 小时的计时要求为24进位，分和秒的计时要求为60进位； 校正时间（小时、分钟）。 扩展功能为： 闹钟（可调整）； 仿广播电台整点报时； 报整点时数。 12/24显示切换2、 总体组成框图：3、 基于Verilog HDL开发的PLD的流程：输入HDL程序对目标器件编程给输入、输出信号分配引脚号选择目标器件仿真测试编译4、 Verilog HDL程序的基本结构：module 模块名 （端口名1，端口名2，端口名3，）； 端口类型说明（input，output，inout）； 参数定义（可选）； 数据类型定义（wire，reg等）； 实体化底层模块和基本门级元件 连续赋值语句（assign）； 过程块结构（initial和always）行为描述语句；endmodule三、实验器件个人计算机 Device : Cyclone EP3C16F484C6四、实验过程1、分级模块 24计数器； 60计数器； 校时器； 分频器； 整点报时、仿电台报时器； 12/24转换器； 译码器。 显示器2、仿真3、编译链接、分配管脚4、下载到DEO板五、数字钟源代码module counter24(CntH, CntL, nCR, EN, CP);/24进制input CP, nCR, EN;output3:0 CntH, CntL;reg3:0 CntH, CntL;reg CO;always (posedge CP or negedge nCR)beginif(nCR) CntH, CntL = 8h00;else if(EN) CntH, CntL 2)|(CntL 9) | (CntH = 2)&(CntL =3)CntH, CntL = 8h00;else if(CntH = 2) & (CntL 3)begin CntH = CntH; CntL = CntL + 1b1; endelse if(CntL = 9)begin CntH = CntH + 1b1; CntL = 4b0000; endelse begin CntH = CntH; CntL = CntL + 1b1; endendendmodulemodule counter12(CntH, CntL, nCR, EN, CP); /12进制input CP, nCR, EN;output3:0 CntH, CntL;reg3:0 CntH, CntL;reg CO;always (posedge CP or negedge nCR)beginif(nCR) CntH, CntL = 8h00;else if(EN) CntH, CntL 1)|(CntL 9) | (CntH = 1)&(CntL =2)CntH, CntL = 8h1;else if(CntH = 1) & (CntL 1)begin CntH = CntH; CntL = CntL + 1b1; endelse if(CntL = 9)begin CntH = CntH + 1b1; CntL = 4b0000; endelse begin CntH = CntH; CntL = CntL + 1b1; endendendmodulemodule counter6(Q, nCR, EN, CP);/6进制input CP, nCR, EN;output3:0 Q;reg3:0 Q;always (posedge CP or negedge nCR)begin if(nCR) Q = 4b0000;else if(EN) Q = Q;else if(Q = 4b0101) Q = 4b0000;else Q = Q + 1b1;endendmodulemodule counter10(Q, nCR, EN, CP);/10进制input CP, nCR, EN;output3:0 Q;reg3:0 Q;always (posedge CP or negedge nCR)beginif(nCR) Q = 4b0000;else if(EN)Q = Q;else if(Q = 4b1001)Q = 4b0000;else Q = Q + 1b1; end endmodulemodule fenpin1(clk_in,clk_out);/分频1hzinput clk_in;output clk_out;reg clk_out;reg 31:0 count;always (posedge clk_in)beginif(count32d24999999)begin count=count+1b1;endelse begincount=32b0;clk_out=clk_out;endendendmodulemodule fenpin10(clk_in,clk_out);/分频10hzinput clk_in;output clk_out;reg clk_out;reg 31:0 count;always (posedge clk_in)beginif(count32d2499999)begin count=count+1b1;endelse begincount=32b0;clk_out=clk_out;endendendmodulemodule led(Sglin,Sglout); /发光二极管计数output3:0 Sglout;input3:0 Sglin;reg3:0 Sglout;wire3:0 Sglin;always (Sglin) begincase(Sglin)4d0:Sglout=4b0000;4d1:Sglout=4b0001;4d2:Sglout=4b0010;4d3:Sglout=4b0011;4d4:Sglout=4b0100;4d5:Sglout=4b0101;4d6:Sglout=4b0110;4d7:Sglout=4b0111;4d8:Sglout=4b1000;4d9:Sglout=4b1001;default:Sglout=4b0000;endcaseendendmodulemodule seg(Din,Seg); /数字显示器译码input3:0 Din;output6:0 Seg;reg6:0 Seg;wire3:0 Din;always (Din) begincase(Din)4d0:Seg=7b1000000;4d1:Seg=7b1111001;4d2:Seg=7b0100100;4d3:Seg=7b0110000;4d4:Seg=7b0011001;4d5:Seg=7b0010010;4d6:Seg=7b0000010;4d7:Seg=7b1111000;4d8:Seg=7b0000000;4d9:Seg=7b0010000;default:Seg=7b1111111;endcaseendendmodulemodule zhengdian(Hour,Minute,Second,Led8,CP1,CP10);/整点报时，仿电台报时input7:0 Hour,Minute,Second;input CP1,CP10;output Led8;wire7:0 Hour,Minute,Second;reg Led8;always (posedge CP10)beginif(Minute7:0=8d0) & (Second7:0Hour7:0)beginLed8=CP1;endelse Led8=0;endendmodulemodule alarm(Hour24,Minute,HSet24,MSet,Led9,CP,K);/闹钟模块input7:0 Hour24,Minute,HSet24,MSet;input CP,K;output Led9;wire7:0 Hour24,Minute,HSet24,MSet;reg Led9;always (posedge CP)beginif(K) Led9=0;else if(HSet247:0=Hour247:0)&(MSet7:0=Minute7:0)Led9=Led9;else Led9=0;endendmodulemodule digclock(SegHH,SegHL,SegMH,SegML, LedH,LedL, Plus, CLK, nCR, EN, Adj_Min, Adj_Hour, SW,SK,K, Led8,Led9); /主模块input CLK, nCR, EN, Adj_Min, Adj_Hour, Plus, SW,SK,K;output6:0 SegHH,SegHL,SegMH,SegML;output3:0 LedH,LedL;output Led8,Led9;supply1 Vdd;supply0 Vss;wire7:0 Hour,Hour12,Hour24, Minute,aMinute, Second,HSet12,HSet24,MSet;wire MinL_EN, MinH_EN, Hour_EN, CP,CP1,CP10;fenpin1 F1(CLK, CP1);fenpin10 F2(CLK, CP10);assign CP = Plus ? CP1 : CP10;counter10 U1(Second3:0, nCR, EN, CP1);counter6 U2(Second7:4, nCR, (Second3:0=4h9), CP1);assign MinL_EN = (SK & Adj_Min) ? Vdd : (Second=8h59);assign MinH_EN = (SK & Adj_Min) & (Minute3:0=4h9)|(Minute3:0=4h9)&(Second=8h59);counter10 U3(Minute3:0, nCR, MinL_EN, CP);counter6 U4(Minute7:4, nCR, MinH_EN, CP);assign Hour_EN = (SK & Adj_Hour) ? Vdd : (Minute = 8h59)&(Second = 8h59);counter24 U5(Hour247:4, Hour243:0, nCR, Hour_EN, CP);counter12 U6(Hour127:4, Hour123:0, nCR, Hour_EN, CP);assign Hour = SW ? (SK ? HSet12:Hour12) :(SK ? HSet24:Hour24);assign aMinute = SK ? MSet: Minute;counter10 U7(MSet3:0, nCR, MSL_EN, CP);counter6 U8(MSet7:4, nCR, MSH_EN, CP);assign MSL_EN = (SK & Adj_Min) ? Vdd : Vss;assign MSH_EN = (SK & Adj_Min) & (MSet3:0=4h9);counter24 U9(HSet247:4, HSet243:0, nCR, HS_EN, CP);counter12 U0(HSet127:4, HSet123:0, nCR, HS_EN, CP);assign HS_EN = (SK & Adj_Hour) ? Vdd : Vss;seg S1(aMinute3:0, SegML);seg S2(aMinute7:4, SegMH);seg S3(Hour3:0, SegHL);seg S4(Hour7:4, SegHH);led L1(Second3:0, LedL);led L2(Second7:4, LedH);zhengdian L3(Hour,Minute,Second,Led8,CP1,CP10);alarm(Hour24,Minute,HSet24,